From Gas Or Vapor, E.g., Condensation (epo) Patents (Class 257/E21.478)
  • Patent number: 8895443
    Abstract: Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Xinliang Lu, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Mei Chang
  • Patent number: 8841211
    Abstract: Methods for forming interconnect structures are provided herein. In some embodiments, a method for forming an interconnect on a substrate may include depositing a material atop an upper surface of the substrate and atop one or more surfaces of a feature disposed in the substrate by a first deposition process that deposits the material at a faster rate on the upper surface than on a bottom surface of the feature; depositing the material atop the upper surface of the substrate and atop one or more surfaces of the feature by a second deposition process that deposits the material at a greater rate on the bottom surface of the feature than on the upper surface of the substrate; and heating the deposited material to draw the deposited material towards the bottom surface of the feature to at least partially fill the feature with the deposited material.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: September 23, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Joung Joo Lee, Xianmin Tang, Tza-Jing Gung
  • Patent number: 8541318
    Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 24, 2013
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
  • Patent number: 8445367
    Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Tae Noh, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
  • Patent number: 8440556
    Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Scott Bruce Clendenning, Niloy Mukherjee
  • Patent number: 8242032
    Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: August 14, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
  • Patent number: 8227358
    Abstract: Novel silicon precursors for low temperature deposition of silicon films are described herein. The disclosed precursors possess low vaporization temperatures, preferably less than about 500° C. In addition, embodiments of the silicon precursors incorporate a —Si—Y—Si— bond, where Y may comprise an amino group, a substituted or unsubstituted hydrocarbyl group, or oxygen. In an embodiment a silicon precursor has the formula: where Y is a hydrocarbyl group, a substituted hydrocarbyl group, oxygen, or an amino group; R1, R2, R3, and R4 are each independently a hydrogen group, a hydrocarbyl group, a substituted hydrocarbyl group, a heterohydrocarbyl group, wherein R1, R2, R3, and R4 may be the same or different from one another; X1, X2, X3, and X4 are each independently, a hydrogen group, a hydrocarbyl group, a substituted hydrocarbyl group, or a hydrazine group, wherein X1, X2, X3, and X4 may be the same or different from one another.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: July 24, 2012
    Assignee: Air Liquide Electronics U.S. LP
    Inventors: Ziyun Wang, Ashutosh Misra, Ravi Laxman
  • Patent number: 8227328
    Abstract: This disclosure relates to the synthesis of Er doped GaN epilayers by in-situ doping by metal-organic chemical vapor deposition (MOCVD). In an embodiment, both above and below bandgap excitation results in a sharp PL emission peak at 1.54 ?m. Contrary with other growth methods, MOCVD grown Er-doped GaN epilayers exhibit virtually no visible emission lines, an present a small thermal quenching effect. The Er incorporation has very little effect on the electrical conductivity of the GaN epilayers and Er doped layers retain similar electrical properties as those of undoped GaN.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: July 24, 2012
    Inventors: Hongxing Jiang, Jingyu Lin, Cris Ugolini, John Zavada
  • Patent number: 8093158
    Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 10, 2012
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Taketoshi Sato, Masayuki Tsuneda
  • Publication number: 20110294284
    Abstract: According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, a nitrogen-based gas and a phosphorous-based gas. The mixture ratio of the nitrogen-based gas to the silicon-based gas among the source gas may be 0.03 or lower (but, excluding zero). Nitrogen in the thin film may be 11.3 atomic percent or lower (but, excluding zero).
    Type: Application
    Filed: April 29, 2009
    Publication date: December 1, 2011
    Inventors: Hai Won Kim, Sang Ho Woo, Sung Gil Cho, Song Hwan Park, Kyung Soo Jung
  • Publication number: 20110151619
    Abstract: A method of forming a metal oxide film, which can lower a temperature of a heat treatment of a substrate and also can form a metal oxide film having a low resistance value without limiting the kind of the metal oxide film to be formed. The method of forming a metal oxide film includes (A) converting a solution containing a metal into mist, (B) heating a substrate, and (C) supplying the solution converted into mist, and ozone to a first main surface of the substrate under heating.
    Type: Application
    Filed: September 24, 2008
    Publication date: June 23, 2011
    Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYS. CORP.
    Inventors: Hiroyuki Orita, Akio Yoshida, Masahisa Kogura, Takahiro Shirahata, Syuji Tanaka
  • Publication number: 20110128668
    Abstract: An electrode of a semiconductor device includes a TiCN layer and a TiN layer. A method for fabricating an electrode of a semiconductor device includes preparing a substrate, forming a TiCN layer, and forming a TiN layer.
    Type: Application
    Filed: June 28, 2010
    Publication date: June 2, 2011
    Inventors: Kwan-Woo DO, Kee-Jeung Lee, Kyung-Woong Park, Jeong-Yeop Lee
  • Publication number: 20110104884
    Abstract: A hot edge ring with extended lifetime comprises an annular body having a sloped upper surface. The hot edge ring includes a step underlying an outer edge of a semiconductor substrate supported in a plasma processing chamber wherein plasma is used to process the substrate. The step includes a vertical surface which surrounds the outer edge of the substrate and the sloped upper surface extends upwardly and outwardly from the upper periphery of the vertical surface.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 5, 2011
    Applicant: Lam Research Corporation
    Inventors: Akira Koshiishi, Sathya Mani, Gautam Bhattacharyya, Gregory R. Bettencourt, Sandy Chao
  • Publication number: 20110104896
    Abstract: There are provided a method of manufacturing a semiconductor device and a substrate processing apparatus, which are designed to prevent deterioration of the surface morphology of a Ni-containing film caused by dependence on an under layer, and to form a continuous film in a thin-film region. The method includes: loading a substrate into a process vessel; heating the substrate in the process vessel; pretreating the heated substrate by supplying a reducing gas into the process vessel and exhausting the reducing gas; removing the reducing gas remaining in the process vessel by supplying an inert gas into the process vessel and exhausting the inert gas; forming a nickel-containing film on the heated and pretreated substrate to a predetermined thickness by supplying a nickel-containing source into the process vessel and exhausting the nickel-containing source; and unloading the substrate from the process vessel.
    Type: Application
    Filed: October 13, 2010
    Publication date: May 5, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Kazuhiro HARADA, Hideharu ITATANI, Sadayoshi HORII
  • Publication number: 20110068470
    Abstract: An apparatus for depositing seed layers over a substrate, which substrate includes a patterned insulating layer with at least one opening surrounded by a field, and which opening has sidewalls, bottom surfaces and top corners, includes: a CVD chamber adapted to deposit one or more CVD seed layers over the substrate; a PVD chamber adapted to deposit one or more PVD seed layers over the substrate; and a controller which includes recipe information. The recipe information includes deposition sequence and process parameters for operation of the deposition chambers.
    Type: Application
    Filed: March 22, 2010
    Publication date: March 24, 2011
    Inventor: URI COHEN
  • Publication number: 20110059600
    Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 10, 2011
    Applicant: HITACHI-KOKUSAI ELECTRIC INC.
    Inventors: Masanori SAKAI, Yukinao KAGA, Takashi YOKOGAWA, Tatsuyuki SAITO
  • Patent number: 7888271
    Abstract: A method for making silicon nano-structure, the method includes the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of catalyst separately into the reacting room. Thirdly, introducing a silicon-containing gas and hydrogen gas into the reacting room. Lastly, heating the reacting room to a temperature of 500˜1100° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: February 15, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Publication number: 20110031593
    Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 10, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Tatsuyuki SAITO, Masanori SAKAI, Yukinao KAGA, Takashi Yokogawa
  • Publication number: 20110027991
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 7863203
    Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 4, 2011
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
  • Publication number: 20100320443
    Abstract: This disclosure relates to the synthesis of Er doped GaN epilayers by in-situ doping by metal-organic chemical vapor deposition (MOCVD). In an embodiment, both above and below bandgap excitation results in a sharp PL emission peak at 1.54 ?m. Contrary with other growth methods, MOCVD grown Er-doped GaN epilayers exhibit virtually no visible emission lines, an present a small thermal quenching effect. The Er incorporation has very little effect on the electrical conductivity of the GaN epilayers and Er doped layers retain similar electrical properties as those of undoped GaN.
    Type: Application
    Filed: August 24, 2007
    Publication date: December 23, 2010
    Inventors: Hongxing Jiang, Jingyu Lin, Cris Ugolini, John Zavada
  • Publication number: 20100255652
    Abstract: According to the invention, a Ti film is formed on a substrate and is annealed at the temperatures of 350° C.-400° C. under oxidative environment, so that a TiO2 film having a rutile crystal structure is formed. Since the TiO2 film having a rutile crystal structure has a high dielectric constant, it is useful for a capacitive insulating film for a capacitor.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 7, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Masami TANIOKU
  • Publication number: 20100248460
    Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 30, 2010
    Inventors: Jin-Il Lee, Urazaev Vladimir, Jin-Ha Jeong, Seung-Back Shin, Sung-Lae Cho, Hyeong-Geun An, Dong-Hyun Im, Jung-Hyeon Kim
  • Patent number: 7803707
    Abstract: The present invention provides metal silicide nanowires, including metallic, semiconducting, and ferromagnetic semiconducting transition metal silicide nanowires. The nanowires are grown using either chemical vapor deposition (CVD) or chemical vapor transport (CVT) on silicon substrates covered with a thin silicon oxide film, the oxide film desirably having a thickness of no greater than about 5 nm and, desirably, no more than about 2 nm (e.g., about 1-2 nm). The metal silicide nanowires and heterostructures made from the nanowires are well-suited for use in CMOS compatible wire-like electronic, photonic, and spintronic devices.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: September 28, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Song Jin, Andrew L. Schmitt, Yipu Song
  • Publication number: 20100233836
    Abstract: A method for manufacturing a ZnO based compound semiconductor device including a contact for a p-type ZnO based compound semiconductor electrode is provided. The method includes forming a stacked body including a substrate, and an n-type ZnO based semiconductor layer and a p-type ZnO based semiconductor layer on the substrate, with the p-type ZnO based semiconductor layer exposed to outside. The stacked body is subjected to heat treatment so that a surface temperature of the p-type ZnO based semiconductor layer is in the range of 250° C. to 500° C. After the heat treatment, a p-side metal electrode is formed on the p-type ZnO based semiconductor layer at a temperature lower than 550° C. And an n-side metal electrode is formed on the n-type ZnO based semiconductor layer.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 16, 2010
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Chizu KYOTANI, Michihiro Sano
  • Patent number: 7790634
    Abstract: Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is generated outside the reaction chamber. The methods also include heating the silicon oxide layer at a temperature of about 600° C. or less, and exposing the silicon oxide layer to an induced coupled plasma. Additional methods are described where the deposited silicon oxide layer is cured by exposing the layer to ultra-violet light, and also exposing the layer to an induced coupled plasma.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: September 7, 2010
    Assignee: Applied Materials, Inc
    Inventors: Jeffrey C. Munro, Srinivas D. Nemani
  • Publication number: 20100213789
    Abstract: An electrostatic drive MEMS (Micro Electro Mechanical Systems) element includes a substrate; a fixed electrode disposed on the substrate; a movable electrode arranged to face the fixed electrode in a vertical direction and be movable toward the fixed electrode through an electrostatic force generated between the fixed electrode and the movable electrode; and an insulation film disposed on one of an upper surface of the fixed electrode and a lower surface of the movable electrode and formed of an insulation member containing a conductive fine particle.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 26, 2010
    Inventor: Yasushi IGARASHI
  • Patent number: 7776742
    Abstract: A TiN film is formed to have a predetermined thickness on a semiconductor wafer by heating the semiconductor wafer at a film formation temperature within a process container and performing a cycle including a first step and a second step at least once. The first step is arranged to supply a TiCl4 gas and a NH3 gas to form a film of TiN by CVD. The second step is arranged to stop the TiCl4 gas and supply the NH3 gas. In film formation, the semiconductor wafer is set at a temperature of less than 450° C. and the process container is set to have therein a total pressure of more than 100 Pa. The NH3 gas is set to have a partial pressure of 30 Pa or less within the process container in the first step.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: August 17, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Toshio Hasegawa
  • Publication number: 20100200954
    Abstract: In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process. An intermediate product comprises a substrate, a plurality of ion implantation regions on the substrate, and a porous capping layer covering the ion implantation regions.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 12, 2010
    Inventors: JOSE IGNACIO DEL AGUA BORNIQUEL, Tze Poon, Robert Schreutelkamp, Majeed Foad
  • Publication number: 20100190331
    Abstract: A method for depositing a film onto a substrate is provided. The substrate is contained within a reactor vessel at a pressure of from about 0.1 millitorr to about 100 millitorr. The method comprises subjecting the substrate to a reaction cycle comprising i) supplying to the reactor vessel a gas precursor at a temperature of from about 20° C. to about 150° C. and a vapor pressure of from about 0.1 torr to about 100 torr, wherein the gas precursor comprises at least one organo-metallic compound; and ii) supplying to the reactor vessel a purge gas, an oxidizing gas, or combinations thereof.
    Type: Application
    Filed: September 15, 2009
    Publication date: July 29, 2010
    Inventors: Steven C. Selbrede, Martin Zucker, Vincent Venturo
  • Publication number: 20100178758
    Abstract: The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 15, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jeng-Hwa Liao, Jung-Yu Hsieh, Ling-Wu Yang
  • Publication number: 20100151676
    Abstract: Embodiments of the present invention provide methods of forming and densifying a titanium nitride barrier layer. The densification process is performed at a relatively low RF plasma power and high nitrogen to hydrogen ratio so as to provide a substantially titanium rich titanium nitride barrier layer. In one embodiment, a method for forming a titanium nitride barrier layer on a substrate includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition process, and performing a plasma treatment process on the deposited titanium nitride layer, wherein the plasma treatment process operates to densify the deposited titanium nitride layer, resulting in a densified titanium nitride layer, wherein the plasma treatment process further comprises supplying a plasma gas mixture containing a nitrogen gas to hydrogen gas ratio between about 20:1 and about 3:1, and applying less than about 500 Watts RF power to the plasma gas mixture.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Alan Alexander Ritchie, Mohd Fadzil Anwar Hassan
  • Publication number: 20100140802
    Abstract: On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a processing gas. The Mn-containing thin film or the CuMn-containing alloy thin film can be formed with high step coverage in a fine recess formed on the surface of the object to be treated.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 10, 2010
    Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Kenji MATSUMOTO, Hitoshi ITOH, Koji NEISHI, Junichi KOIKE
  • Publication number: 20100144135
    Abstract: A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 10, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Kwon, Young-Soo Lim, Sung-Un Kwon, Yong-Ho Ha, Jeong-Hee Park, Joon-Sang Park, Myung-Jin Kang, Doo-Hwan Park
  • Publication number: 20100136773
    Abstract: A semiconductor device manufacturing method comprises the steps of loading a substrate into a processing chamber, mounting the substrate on a support tool in the processing chamber, processing the substrate mounted on the support tool by supplying process gas into the processing chamber, purging the interior of the processing chamber after the substrate processing step, and unloading the processed substrate from the processing chamber after the step of purging the interior of the processing chamber, wherein in the step of purging the interior of the processing chamber, exhaust is performed toward above the substrate and toward below the substrate in the processing chamber, and the exhaust rate toward above the substrate is set larger than the exhaust rate toward below the substrate.
    Type: Application
    Filed: August 4, 2006
    Publication date: June 3, 2010
    Inventors: Naonori Akae, Masahiro Yonebayashi, Tsukasa Kamakura, Yoshiro Hirose
  • Patent number: 7713886
    Abstract: Disclosed is a film forming method using a film forming gas composed of a metal alkoxide wherein clean film formation suppressed in contamination of a target substrate to be processed is achieved by restraining aluminum or an aluminum alloy in the processing chamber from dissolving. Specifically disclosed is method for forming a thin film on a target substrate to be processed which is held in a processing chamber, and this method comprises a step for heating the target substrate and a step for supplying a film forming gas into the processing chamber. This method is characterized in that the film forming gas is composed of a metal alkoxide, the processing chamber is made of aluminum or an aluminum alloy, and a protective film composed of a nonporous anodic oxide film is formed on the inner wall surface of the processing chamber.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: May 11, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Hirokatsu Kobayashi, Tetsuya Nakano, Masato Koizumi
  • Publication number: 20100105192
    Abstract: A method of manufacturing a semiconductor device includes: forming an oxide film having a predetermined film thickness on a substrate by repeating a process of forming a predetermined element-containing layer on the substrate by supplying source gas containing a predetermined element into a process vessel accommodating the substrate, and a process of changing the predetermined element-containing layer to an oxide layer by supplying oxygen-containing gas and hydrogen-containing gas into the process vessel that is set below atmospheric pressure, wherein the oxygen-containing gas is oxygen gas or ozone gas, the hydrogen-containing gas is hydrogen gas or deuterium gas, and the temperature of the substrate is in a range from 400° C. or more to 700° C. or less in the process of forming the oxide film.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 29, 2010
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Publication number: 20100075475
    Abstract: An electrode is prevented from being peeled from a substrate or a silicon layer. After the surface of a first copper thin film composed mainly of copper is treated by exposing it to an ammonia gas, a film of silicon nitride is formed on the surface of the first copper thin film by generating a plasma of a raw material gas containing a silane gas and an ammonia gas in an atmosphere in which an object to be processed is placed. Since the surface is preliminarily treated with the ammonia gas, the silane gas is prevented from being diffused into the first copper thin film. Therefore, an electrode constituted by the surface-treated first copper thin film is not peeled from the glass substrate or the silicon layer. In addition, its electric resistance value does not rise.
    Type: Application
    Filed: December 3, 2009
    Publication date: March 25, 2010
    Applicant: ULVAC, INC.
    Inventors: Satoru TAKASAWA, Yuuichi Oishi, Miho Shimizu, Tooru Kikuchi, Satoru Ishibashi
  • Patent number: 7651961
    Abstract: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the silicon precursor with a second reactivity characteristic such that a property of the silicon nitride film formed on the substrate changes to provide the strained silicon nitride film.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: January 26, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 7642099
    Abstract: A manufacturing method for a ferroelectric memory device includes: forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode; forming a first hydrogen barrier film that covers the ferroelectric capacitor by a chemical vapor deposition method; forming a dielectric film on the first hydrogen barrier film; forming a sidewall composed of the dielectric film on a side of the ferroelectric capacitor by etching back the dielectric film; forming a second hydrogen barrier film on the first hydrogen barrier film and the sidewall by a chemical vapor deposition method; and forming an interlayer dielectric film on the second hydrogen barrier film.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: January 5, 2010
    Assignees: Seiko Epson Corporation, Fujtisu Limited
    Inventors: Shinichi Fukada, Naoya Sashida
  • Publication number: 20090275197
    Abstract: A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are introduced into a reaction chamber to thereby form a first tungsten layer. Subsequently, at least one of H2 gas and inert gas is introduced into the reaction chamber, the temperature of the semiconductor substrate is raised to equal to or more than 370° C. and equal to or less than 410° C. with 30 or more seconds, and tungsten-containing gas is introduced into the reaction chamber to thereby form a second tungsten layer on the first tungsten layer.
    Type: Application
    Filed: January 9, 2009
    Publication date: November 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: ATSUSHI KARIYA
  • Publication number: 20090263967
    Abstract: A noble metal layer is formed using ozone (O3) as a reaction gas.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 22, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Deok-Sin Kil, Kee-Jeung Lee, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park, Jeong-Yeop Lee, Ja-Yong Kim
  • Patent number: 7605078
    Abstract: A method for forming a variable thickness Cu seed layer on a substrate for a subsequent Cu electrochemical plating process, where the Cu seed layer thickness profile improves uniformity of the electroplated Cu layer compared to when using a constant thickness Cu seed layer. The method includes depositing a Ru metal layer on the substrate, depositing a variable thickness Cu seed layer on the Ru metal layer by a physical vapor deposition process, whereby the variable thickness Cu seed layer is deposited with a Cu thickness at the edge of the substrate that is less than a Cu thickness at the center of the substrate, and plating bulk Cu onto the variable thickness Cu seed layer. The Ru metal layer may be a variable thickness Ru metal layer, or alternately, the Ru metal layer may have a substantially uniform Ru metal thickness across the substrate.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 20, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Kenji Suzuki
  • Patent number: 7592257
    Abstract: The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature and on the contact layer. The method further includes forming an oxidation-resistant diffusion barrier by increasing the nitrogen-content of the deposited metal carbonitride or metal carbide film, depositing a Ru film on the oxidation-resistant diffusion barrier, and forming bulk Cu metal in the micro-feature. A semiconductor contact structure is described.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: September 22, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Tadahiro Ishizaka
  • Patent number: 7592254
    Abstract: The present invention provides methods for conformally or superconformally coating and/or uniformly filling structures with a continuous, conformal layer or superconformal layer. Methods of the present invention improve conformal or superconformal coverage of surfaces and improve fill in recessed features compared to conventional physical deposition and chemical deposition methods, thereby minimizing formation of voids or gaps in a deposited conformal or superconformal layer. The present methods are capable of coating or filling features useful for the fabrication of a broad class of electronic, electrical and electromechanical devices.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 22, 2009
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John R. Abelson, Sreenivas Jayaraman, Gregory S. Girolami, Yu Yang, Do Young Kim
  • Patent number: 7585789
    Abstract: A method of forming a porous film on a semiconductor substrate includes: supplying a silicon compound containing at least one Si—O bond in its molecule in a gaseous phase into a reaction chamber; forming a siloxane oligomer through plasma reaction of the silicon compound; and supplying an organic amine in a gaseous phase into the reaction chamber and reacting the organic amine with the siloxane oligomer, thereby forming a porous film on the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: September 8, 2009
    Assignees: ASM Japan K.K., Ulvac, Inc., NEC Corporation
    Inventors: Yasuyoshi Hyodo, Kazuo Kohmura, Nobutoshi Fujii, Nobutaka Kunimi, Keizo Kinoshita
  • Publication number: 20090221139
    Abstract: A method of producing a semiconductor device includes the steps of: forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film; patterning the gate electrode layer to form a gate electrode; and processing thermally the gate electrode layer or the gate electrode under an oxidation environment. Further, the gate electrode layer or the gate electrode is thermally processed under the oxidation environment at a temperature between 750° C. and 900° C.
    Type: Application
    Filed: February 19, 2009
    Publication date: September 3, 2009
    Inventor: Toru Yoshie
  • Patent number: 7575944
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor LED including sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate; forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer; heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed; removing the Pd/Zn alloy layer formed on the p-type nitride semiconductor layer; mesa-etching portions of the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sun Woon Kim, Seong Ju Park, Ja Yeon Kim, Min Ki Kwon, Dong Ju Lee, Jae Ho Han
  • Patent number: 7572647
    Abstract: A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end. The first end of the coil segment is adapted to connect to a power source. The second coil segment has a first and second end. The second end of the first coil segment is adapted to connect to an external balance capacitor. The internal balance capacitor is connected in series between the second end of the first coil segment and the first end of the second coil segment. The internal balance capacitor and the coil segments are adapted to provide a voltage peak along the first coil segment substantially aligned with a virtual ground along the second coil segment.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: August 11, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Robert Chen, Canfeng Lai, Xinglong Chen, Weiyi Luo, Zhong Qiang Hua, Siqing Lu, Muhammad Rasheed, Qiwei Liang, Dmitry Lubomirsky, Ellie Y. Yieh
  • Publication number: 20090197410
    Abstract: A substrate is disposed in a processing chamber. An organic Ta compound gas having Ta?N bond, a Si-containing gas and a N-containing gas are introduced into the processing chamber to form a TaSiN film on the substrate by CVD. In this film formation, at least one of a partial pressure of the Si-containing gas in the processing chamber, a total pressure in the processing chamber, a film forming temperature and a partial pressure of the N-containing gas in the processing chamber is controlled to thereby regulate Si concentration in the film. Particularly, when SiH4 gas is used as the Si-containing gas, the SiH4 gas partial pressure is determined based on the fact that the serried Si concentration in the film under giving process conditions can be expressed as a linear function involving the logarithm of the partial pressure of the SiH4 gas.
    Type: Application
    Filed: June 21, 2007
    Publication date: August 6, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuhito Nakamura, Hideaki Yamasaki, Yumiko Kawano