To Change Their Surface-physical Characteristics Or Shape, E.g., Etching, Polishing, Cutting (epo) Patents (Class 257/E21.483)
  • Patent number: 9748415
    Abstract: A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 29, 2017
    Assignee: Sandia Corporation
    Inventors: Murat Okandan, Gregory N. Nielson, Jose Luis Cruz-Campa, Carlos Anthony Sanchez
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 9034733
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 8836129
    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Patent number: 8828891
    Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Takeshi Sakamoto
  • Patent number: 8809968
    Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: August 19, 2014
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Oliver Hilt, Rimma Zhytnytska, Hans-Joachim Würfl
  • Patent number: 8778715
    Abstract: A method of making a neutron detector such as a microstructured semiconductor neutron detector is provided. The method includes the step of providing a particle-detecting substrate having a surface and a plurality of cavities extending into the substrate from the surface. The method also includes filling the plurality of cavities with a neutron-responsive material. The step of filling including the step of centrifuging nanoparticles of the neutron-responsive material with the substrate for a time and a rotational velocity sufficient to backfill the cavities with the nanoparticles. The material is responsive to neutrons absorbed, thereby, for releasing ionizing radiation reaction products.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Radiation Detection Technologies, Inc.
    Inventors: Steven L. Bellinger, Ryan G. Fronk, Douglas S. McGregor
  • Patent number: 8759228
    Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Wilson, Mark Kiehlbauch
  • Patent number: 8709915
    Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 29, 2014
    Inventor: Takeo Tsukamoto
  • Patent number: 8703551
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Andreas Ott
  • Patent number: 8669190
    Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Togo, Hiroaki Sano
  • Patent number: 8664089
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
  • Patent number: 8592316
    Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Takehiro Yoshida
  • Patent number: 8580597
    Abstract: A method for making a microelectronic device including, on a same substrate, at least one electro-mechanical component including a mobile structure of a monocrystalline semi-conductor material and a mechanism actuating and/or detecting the mobile structure, and with at least one transistor. The method a) provides a substrate including at least one first semi-conducting layer including at least one region in which a channel area of the transistor is provided, b) etches a second semi-conducting layer based on a given semi-conductor material, lying on an insulating layer placed on the first semi-conducting layer, to form at least one pattern of the mobile structure of the component in an area of monocrystalline semi-conductor material of the second semi-conducting layer, and at least one pattern of gate of the transistor on a gate dielectric area located facing the given region.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 12, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Eric Ollier, Audrey Berthelot
  • Patent number: 8569180
    Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 29, 2013
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8536025
    Abstract: A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dennis P. Hogan, Gregory S. Jankowski, Robert K. Leidy
  • Patent number: 8501521
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a copper species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 6, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8486761
    Abstract: A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Serge J. Bierhuizen
  • Patent number: 8487296
    Abstract: Methods, devices, systems and/or articles related to techniques for forming a graphene film on a substrate, and the resulting graphene layers and graphenated substrates are generally disclosed. Some example techniques may be embodied as methods or processes for forming graphene. Some other example techniques may be embodied as devices employed to manipulate, treat, or otherwise process substrates, graphite, graphene and/or graphenated substrates as described herein. Graphene layers and graphenated substrates produced by the various techniques and devices provided herein are also disclosed.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 16, 2013
    Assignee: New Jersey Institute of Technology
    Inventors: Haim Grebel, Amrita Banerjee
  • Patent number: 8476104
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 2, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8435826
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method forms a bulk copper indium disulfide material from a multi-layered structure comprising a copper species, an indium species, and a sulfur species overlying the first electrode layer. The bulk copper indium disulfide material comprises one or more portions of a copper poor copper indium disulfide material, a copper poor surface regions, and one or more portions of a sulfur deficient copper indium disulfide material characterized by at least a CuInS2-x species, where 0<x<2. The copper poor surface and one or more portions of the copper poor copper indium disulfide material are subjected to a sodium species derived from a sodium sulfide material to convert the copper poor surface from an n-type characteristic to a p-type characteristic.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 7, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8415235
    Abstract: In a conventional adhesive sheet laminated with a die attachment film, the die attachment film sometimes drops off from the die chip at the time of pick-up after die chip formation by dicing a wafer. The present invention provides an adhesive including a (meth)acrylate ester polymer, a urethane acrylate oligomer having 4 or more vinyl groups, and silicone microparticles. Another aspect of the invention, provides a process for producing electronic components, the process including: a wafer-pasting step of pasting a wafer on a surface of a die attachment film of an adhesive sheet; a dicing step of dicing the wafer into die chips; and a pick-up step of peeling the die attachment film from the adhesive layer after the dicing step, and picking up the die chip together with the die attachment film.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: April 9, 2013
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Satoru Kawata, Takeshi Saito
  • Patent number: 8394662
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: March 12, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8390129
    Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, including a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying the position and direction on the backside surface. Thus, the redistribution layer (RBL) or the special equipment for achieving the backside alignment (BSA) is not necessary.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Hui-Shan Chang, Chung-Hsi Wu, Meng-Jen Wang
  • Patent number: 8389412
    Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: March 5, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
  • Patent number: 8324081
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 4, 2012
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Publication number: 20120241941
    Abstract: A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, YongHee Kang, KyungHoon Lee
  • Patent number: 8273666
    Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: September 25, 2012
    Assignee: MagIC Technologies, Inc.
    Inventors: Rongfu Xiao, Cheng T. Horng, Ru-Ying Tong, Chyu-Jinh Torng, Tom Zhong, Witold Kula, Terry Kin Ting Ko, Wei Cao, Wai-Ming J. Kan, Liubo Hong
  • Patent number: 8273654
    Abstract: Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. An electrically insulating material layer is deposited over a portion of the gate material layer stack and over a portion of the substrate. A patterned deposition inhibiting material is deposited over the electrically insulating material layer. A semiconductor material layer is deposited over the electrically insulating material layer using a selective area deposition process in which the semiconductor material layer is not deposited over the patterned deposition inhibiting material.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 25, 2012
    Assignee: Eastman Kodak Company
    Inventors: Shelby F. Nelson, David H. Levy, Lee W. Tutt
  • Publication number: 20120223308
    Abstract: The present invention provides a thin-film transistor capable of high-speed operation, a process for producing the same, and a display device including the same. The thin-film transistor of the present invention includes, on a substrate, in the order of: a gate electrode; a gate insulating film; an oxide semiconductor film; and a protective insulating film, the protective insulating film having a planar shape that is completely or substantially the same as the planar shape of the gate electrode.
    Type: Application
    Filed: June 17, 2010
    Publication date: September 6, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Publication number: 20120220134
    Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Inventors: Yen-Chu Chen, Teng-Chun Tsai, Chien-Chung Huang, Keng-Jen Liu
  • Publication number: 20120208321
    Abstract: Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: NORDSON CORPORATION
    Inventors: David Keating Foote, James Donald Getty
  • Patent number: 8236611
    Abstract: A method is disclosed for singulating die from a substrate having a sacrificial layer and one or more device layers, with a retainer being formed in the device layer(s) and anchored to the substrate. Deep Reactive Ion Etching (DRIE) etching of a trench through the substrate from the bottom side defines a shape for each die. A handle wafer is then attached to the bottom side of the substrate, and the sacrificial layer is etched to singulate the die and to form a frame from the retainer and the substrate. The frame and handle wafer, which retain the singulated die in place, can be attached together with a clamp or a clip and to form a package for the singulated die. One or more stops can be formed from the device layer(s) to limit a sliding motion of the singulated die.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: August 7, 2012
    Assignee: Sandia Corporation
    Inventors: Robert C. Anderson, Randy J. Shul, Peggy J. Clews, Michael S. Baker, Maarten P. De Boer
  • Patent number: 8222155
    Abstract: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the etchant gas mixture being configured to etch the given layer. The method additionally includes striking a plasma from the etchant source gas. Furthermore, the method includes etching the feature at least partially through the given layer while applying a bias RF signal to the substrate, the bias RF signal having a bias RF frequency of between about 45 MHz and about 75 MHz. The bias RF signal further has a bias RF power component that is configured to cause the etch feature to be etched with an etch selectivity to a second layer of the substrate that is higher than a predefined selectivity threshold.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: July 17, 2012
    Assignee: Lam Research Corporation
    Inventors: Kenji Takeshita, Odette Turmel, Felix Kozakevich, Eric Hudson
  • Patent number: 8187907
    Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: May 29, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventor: Fred Newman
  • Publication number: 20120129351
    Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Anthony Konecni, Josephine Juhwei Liu, Deenesh Padhi, Bok Hoen Kim, William H. Mc Clintock
  • Patent number: 8178439
    Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhito Tohnoe, Frank M. Cerio, Jr.
  • Patent number: 8178425
    Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: May 15, 2012
    Assignee: Disco Corporation
    Inventors: Tasuku Koyanagi, Hiroshi Morikazu
  • Publication number: 20120108043
    Abstract: A resist pattern is formed by coating a first positive resist composition comprising a polymer comprising 20-100 mol % of aromatic group-containing recurring units and adapted to turn alkali soluble under the action of an acid onto a substrate to form a first resist film, coating a second positive resist composition comprising a C3-C8 alkyl alcohol solvent which does not dissolve the first resist film on the first resist film to form a second resist film, exposing, baking, and developing the first and second resist films simultaneously with a developer.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 3, 2012
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Kenji Funatsu
  • Patent number: 8153511
    Abstract: It is an object to improve a yield of a step of cutting off a substrate. A substrate is cut off by using an ablation process. An ablation process uses a phenomenon in which a molecular bond in a portion irradiated with a laser beam, that is, a portion which absorbs the laser beam is cut off, photodegraded, and evaporated. In other words, a substrate is irradiated with a laser beam, a molecular bond in a portion of the substrate is cut off, photodegraded, and evaporated; accordingly, a groove is formed in the substrate. A method for cutting the substrate has steps of selectively emitting a laser beam and forming a groove in the substrate, and selectively emitting a laser beam to the groove and cutting off the substrate. Methods for manufacturing a groove in a substrate and cutting off a substrate are used for manufacturing a semiconductor device.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: April 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daiki Yamada, Naoto Kusumoto
  • Patent number: 8129287
    Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Suzuki, Hidemitsu Aoki
  • Patent number: 8093157
    Abstract: Removing photoresist from a workpiece is described when a region of tungsten is exposed. A plasma is generated from a gas input consisting essentially of hydrogen gas and oxygen gas in a predetermined ratio. The plasma causes the photoresist to be removed from the workpiece while the region of tungsten is left substantially unmodified. The ratio of the hydrogen to oxygen can be adjusted to a particular value which causes the photoresist to be removed at about a maximum removal rate that corresponds to a minimum tungsten loss rate of about zero. Polysilicon oxidation in the presence of tungsten is described with little or no tungsten loss.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: January 10, 2012
    Assignee: Mattson Technology, Inc.
    Inventors: Li Diao, Songlin Xu
  • Patent number: 8080477
    Abstract: A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited on a predetermined region in a gas route from a film formation gas supply system, which supplies a film formation gas contributory to film formation, through the reaction chamber to an exhaust system, by alternately repeating an etching step and an exhaust step a plurality of times in a state where the reaction chamber does not accommodate the target substrate. The etching step includes supplying a cleaning gas in an activated state for etching the by-product film onto the predetermined region, thereby etching the by-product film. The exhaust step includes stopping supply of the cleaning gas and exhausting gas by the exhaust system from a space in which the predetermined region is present.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: December 20, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Nobutake Nodera, Jun Sato, Masanobu Matsunaga, Kazuhide Hasebe
  • Patent number: 8048776
    Abstract: A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: November 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Yaojian Lin, Rui Huang
  • Publication number: 20110217806
    Abstract: An electrode (3i) of a radiofrequency parallel plate plasma reactor comprises an electrode surface of a multitude of surfaces of metal members (28) which reside on dielectric spacing members (29), whereby the metal members (28) are mounted in an electrically floating manner. The dielectric members (29) are mounted, opposite to the metal members (28), upon a metal Rf supply body (14a).
    Type: Application
    Filed: September 28, 2009
    Publication date: September 8, 2011
    Applicant: OERLIKON SOLAR AG, TRUEBBACH
    Inventor: Stephan Jost
  • Patent number: 7999362
    Abstract: A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 16, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hannes Mio, Horst Groeninger, Hermann Vilsmeier
  • Patent number: 7998837
    Abstract: A method for fabricating a semiconductor device using optical proximity correction to form high integrated cell patterns that are less prone to bridge defects. The method includes: obtaining a target layout of cell patterns, which form rows in a cell region, and peripheral patterns of a peripheral region; forming oblique patterns, which are alternately overlapped in the rows of the cell patterns, and a reverse pattern of the peripheral patterns; attaching spacers to sidewalls of the oblique patterns and the reverse pattern; forming first burying patterns between the oblique patterns and a second burying pattern around the reverse pattern by filling gaps between the spacers; and forming the cell patterns by cutting and dividing the middle portions of the oblique patterns and the first burying patterns, and setting the peripheral pattern with the second burying pattern by removing the reverse pattern.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chun Soo Kang
  • Publication number: 20110177693
    Abstract: Gas mixtures which comprise acids like HF, HCl or HBr and other constituents, especially gas mixtures which comprise or consist of carboxylic acid fluorides, C(O)F2 or phosphorous pentafluoride and HCl and optionally HF, can be separated by ionic liquids. The process is performed reversibly. Ionic liquids are applied the anion of which corresponds to a stronger acid than the acid to be removed. Highly purified products, for example, highly purified carbonyl fluoride can be obtained.
    Type: Application
    Filed: April 1, 2011
    Publication date: July 21, 2011
    Applicant: SOLVAY FLUOR GMBH
    Inventors: Jens Olschimke, Carsten Brosch, Andreas Grossmann
  • Publication number: 20110151669
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu