Assembling Semiconductor Devices, E.g., Packaging , Including Mounting, Encapsulating, Or Treatment Of Packaged Semiconductor (epo) Patents (Class 257/E21.499)

  • Patent number: 8946743
    Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 3, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Bong Kul Min
  • Patent number: 8945986
    Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8945990
    Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Holger Torwesten, Manfred Mengel, Stefan Schmid, Soon Lock Goh, Swee Kah Lee
  • Patent number: 8946610
    Abstract: The present invention provides a CMOS type semiconductor image sensor module in which the aperture ratio of the pixel is improved and at the same time chip use efficiency is attempted to be improved and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same. The semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip including an image sensor in which a plurality of pixels, each constituted by a photoelectric conversion element and transistors, are arranged, and a second semiconductor chip including an A/D converter array. Preferably, a third semiconductor chip including a memory element array is further laminated. Also, a semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip provided with the aforesaid image sensor and a fourth semiconductor chip provided with an analog type nonvolatile memory array.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Makoto Motoyoshi
  • Patent number: 8941212
    Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 8941193
    Abstract: A simple and cost-effective manufacturing method for hybrid integrated components including at least one MEMS element, a cap for the micromechanical structure of the MEMS element, and at least one ASIC substrate, using which a high degree of miniaturization may be achieved. The micromechanical structure of the MEMS element and the cap are manufactured in a layered structure, proceeding from a shared semiconductor substrate, by applying at least one cap layer to a first surface of the semiconductor substrate, and by processing and structuring the semiconductor substrate proceeding from its other second surface, to produce and expose the micromechanical MEMS structure. The semiconductor substrate is then mounted with the MEMS-structured second surface on the ASIC substrate.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: January 27, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Jens Frey, Frank Fischer
  • Patent number: 8940630
    Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: January 27, 2015
    Assignee: Invensas Corporation
    Inventors: Philip Damberg, Zhijun Zhao, Ellis Chau
  • Patent number: 8941222
    Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: January 27, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: John Richard Hunt
  • Patent number: 8941177
    Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charlotte DeWan Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 8940562
    Abstract: The present disclosure provides the ability to produce backplanes for AMLCD and AMOLED. Specifically, each and every component of the backplanes can be printed. Depending on the resolution and screen size of the displays, backplanes can include over a million different components that must be printed that include components of the thin film transistor (TFT) and electrodes to address each of those TFTs. Even a slight misregistry of components during printing can lead to failure of one or more pixels, potentially rendering the entire display unsuitable for use. The present disclosure provides the ability to reproducibly and accurately print each and every component of the backplane for both AMLCD and AMOLED. The ability to completely print backplanes provides numerous advantages, such as reduced costs, improved throughput, more environmental friendliness, and the like.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 27, 2015
    Assignee: Atom Nanoelectronics, Inc
    Inventor: Huaping Li
  • Patent number: 8936955
    Abstract: An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 20, 2015
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang, Ya-Wen Lin
  • Patent number: 8936966
    Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8937328
    Abstract: A light emitting device includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the equation, ((M1?x1Eux1)3?ySi13?zAl3+zO2+uN21?w), and an average particle diameter of 12 ?m or more, wherein in the equation, M is an element that is selected from IA group elements, IIA group elements, IIIA group elements, IIIB group elements except Al, rare-earth elements, and IVB group elements, and x1, y, z, u, and w satisfy each of the inequalities simultaneously, that is to say each of the following inequalities is satisfied by the choice of values of the identified paramaters within the noted ranges of 0<x1<1, ?0.1<y<0.3, ?3<z?1, ?3<u?w?1.5, 2<u, w<21.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Mitsuishi, Yumi Fukuda, Aoi Okada, Naotoshi Matsuda, Shinya Nunoue, Keiko Albessard, Masahiro Kato
  • Patent number: 8937382
    Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, John S. Guzek
  • Patent number: 8937390
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Patent number: 8937393
    Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • Patent number: 8932906
    Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dean Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsiun Lee
  • Patent number: 8927333
    Abstract: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Shu Lin, Yu-Ling Tsai, Han-Ping Pu
  • Patent number: 8927341
    Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 6, 2015
    Assignee: Nichia Corporation
    Inventors: Masafumi Kuramoto, Satoru Ogawa, Miki Niwa
  • Patent number: 8921990
    Abstract: A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyol Park, Yun-Hyeok Im
  • Patent number: 8922013
    Abstract: An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 30, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: How Yuan Hwang, Kah Wee Gan
  • Patent number: 8916474
    Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef H•glauer
  • Patent number: 8912659
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyeong Seok Choi
  • Patent number: 8912643
    Abstract: An integrated circuit device including a die with a substrate with a first surface and a second surface opposite the first surface is provided. The die includes at least one circuit element positioned on the first surface. Formed on the second surface, is a wetting feature that includes an array of spaced-apart nanoscale structures and/or an array of spaced-apart microscale structures. The wetting feature also includes a wettability coating applied to at least a portion of the second surface. The integrated circuit device includes a spacer coupled to the die adjacent to the second surface. In addition, an injector plate is coupled to the spacer. The injector plate includes at least one microjet and at least one exit hole defined through the injector plate. The at least one exit hole is positioned adjacent to the at least one microjet.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: December 16, 2014
    Assignee: General Electric Company
    Inventors: Hendrik Pieter Jacobus de Bock, Stanton Earl Weaver, Jr., Raj Bahadur, Eric Ayres Browne, Gary Dwayne Mandrusiak
  • Patent number: 8912540
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 16, 2014
    Assignee: Renesas Electronics Corporations
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 8907480
    Abstract: A chip arrangement may include: a first chip including a first contact, a second contact, and a redistribution structure electrically coupling the first contact to the second contact; a second chip including a contact; and a plurality of interconnects electrically coupled to the second contact of the first chip, wherein at least one interconnect of the plurality of interconnects electrically couples the second contact of the first chip to the contact of the second chip.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 9, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Hans-Joachim Barth, Reinhard Mahnkopf, Sven Albers, Andreas Augustin, Christian Mueller
  • Patent number: 8907390
    Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: December 9, 2014
    Assignee: Crocus Technology Inc.
    Inventor: Jason Reid
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8907354
    Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andrew Ingle
  • Patent number: 8906741
    Abstract: A method for making an electronic package structure is provided which comprises: providing a substrate; providing an inductor module; assembling the inductor module and the substrate so that they define a space; injecting package glue into the space defined by the inductor module and the substrate so as to form a package layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 9, 2014
    Assignee: Cyntec Co., Ltd.
    Inventors: Bau-Ru Lu, Kai-Peng Chiang, Da-Jung Chen, Tsung-Chan Wu
  • Patent number: 8907481
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8907469
    Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8901679
    Abstract: A micromechanical structure, in particular a sensor arrangement, includes at least one micromechanical functional layer, a CMOS substrate region arranged below the at least one micromechanical functional layer, and an arrangement of one or more contact elements. The CMOS substrate region has at least one configurable circuit arrangement. The arrangement of one or more contact elements is arranged between the at least one micromechanical functional layer and the CMOS substrate region and is electrically connected to the micromechanical functional layer and the circuit arrangement. The configurable circuit arrangement is designed in such a way that the one or more contact elements are configured to be selectively connected to electrical connection lines in the CMOS substrate region.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Johannes Classen, Mirko Hattass, Lars Tebje, Daniel Christoph Meisel
  • Patent number: 8895994
    Abstract: An electronic device may include an elongated dielectric substrate having opposing first and second ends, a plurality of conductive pads longitudinally spaced apart along the elongated dielectric substrate, and a plurality of silicon carbide (SiC) (e.g., PiN) diode dies. Each SiC die may have bottom and top diode terminals and may be mounted on a respective conductive pad with the bottom diode terminal in contact therewith. The electronic device may further include at least one internal wirebond between the corresponding conductive pad of one SiC diode die and the top diode terminal of a next SiC diode die, a first external lead electrically coupled to the top diode terminal of a first SiC die and extending longitudinally outwardly from the first end, and a second external lead electrically coupled to the corresponding contact pad of a last SiC diode die and extending longitudinally outwardly from the second end.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: November 25, 2014
    Assignee: Schlumberger Technology Corporation
    Inventor: Luke Perkins
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu
  • Patent number: 8889483
    Abstract: A method of manufacturing a semiconductor device in one exemplary embodiment includes preparing a first substrate and a second substrate, the first substrate including a bump electrode group formed of bump electrodes arrayed with a certain pitch, the number of bump electrodes along a first direction being larger than the number of bump electrodes along a second direction perpendicular to the first direction; joining the first substrate and the second substrate to each other through the bump electrodes so that a gap is formed between the first substrate and the second substrate; and filling the gap with a mold resin by causing the mold resin to flow in the gap from an edge of the first substrate along the second direction of the bump electrode group.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Masahito Yamato
  • Patent number: 8884314
    Abstract: The present disclosure is directed to circuitry configurable based on device orientation. Example circuitry may comprise at least one device location and configurable conductors. The at least one device location may include at least two conductive pads onto which a device may be populated by a manufacturing process. The configurable conductors may be coupled to each of the at least two conductive pads. The configurable conductors may be configured by adding conductive material to at least one configurable conductor or subtracting at least part of at least one configurable conductor. For example, conductive material may be added to close a space between two segments of a configurable conductor to form a conduction path. Alternatively, at least part of at least one of a plurality of configurable conductors coupled to a conductive pad may be subtracted (e.g., cut) to stop conduction in the at least one configurable conductor.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 11, 2014
    Assignee: OSRAM SYLVANIA Inc.
    Inventor: Jeffery J. Serre
  • Patent number: 8884343
    Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard Lange, Juergen Neuhaeusler
  • Patent number: 8883536
    Abstract: Systems and methods for a pressure sensor are provided, where the pressure sensor comprises a housing having a high side input port that allows a high pressure media to enter a high side of the housing and a low side input port that allows a low pressure media to enter a low side of the housing when the housing is placed in an environment containing the high and low pressure media; a substrate mounted within the housing; a stress isolation member mounted to the substrate; a die stack having sensing circuitry bonded to the stress isolation member; a low side atomic layer deposition (ALD) applied to surfaces, of the substrate, the stress isolation member, and the die stack, exposed to the low side input port; and a high side ALD applied to surfaces, of the stress isolation member and the die stack, exposed to the high side input port.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: November 11, 2014
    Assignee: Honeywell International Inc
    Inventor: Gregory C. Brown
  • Patent number: 8884347
    Abstract: The present disclosure provides a method of manufacturing a photoelectric conversion device, including, a first step of forming a plurality of photoelectric conversion regions on a surface on one side of a semiconductor wafer, a second step of preparing a light-blocking wafer having insertion openings, a third step of bonding the one-side surface of the semiconductor wafer and a surface on the opposite side to a surface on the one side of the light-blocking wafer to each other to form a bonded wafer body, and a fourth step of dividing the bonded wafer body in peripheries of the photoelectric conversion regions, to obtain bonded-body chips each having the photoelectric conversion region.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventor: Yasuhide Nihei
  • Patent number: 8878216
    Abstract: A light emitting diode (LED) module includes a substrate, an LED disposed on the substrate, a phosphor layer disposed on the LED, and a lens disposed on the substrate. The substrate has a recess defined therein. The lens is fastened to the substrate through the recess. A manufacturing method for the LED includes forming the recess in the substrate, mounting the LED on the substrate, forming the phosphor layer on the LED, and forming the lens directly on the substrate such that the lens is fastened to the substrate through the recess.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Sung You
  • Patent number: 8878367
    Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: November 4, 2014
    Assignee: Xintec Inc.
    Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung
  • Patent number: 8877567
    Abstract: A semiconductor device has an interposer frame having a die attach area. A uniform height insulating layer is formed over the interposer frame at corners of the die attach area. The insulating layer can be formed as rectangular or circular pillars at the corners of the die attach area. The insulating layer can also be formed in a central region of the die attach area. A semiconductor die has a plurality of bumps formed over an active surface of the semiconductor die. The bumps can have a non-fusible portion and fusible portion. The semiconductor die is mounted over the insulating layer which provides a uniform standoff distance between the semiconductor die and interposer frame. The bumps of the semiconductor die are bonded to the interposer frame. An encapsulant is deposited over the semiconductor die and interposer frame and between the semiconductor die and interposer frame.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungHoon Lee, Soo Moon Park, SeungWon Kim
  • Patent number: 8872180
    Abstract: A production method for a liquid crystal display device having a plurality of thin film transistors (TFTs) including reflection sections disposed to correspond to a plurality of pixels includes: a step of forming on a substrate a metal layer having apertures; a step of forming a semiconductor layer on the metal layer; a step of forming a protection layer on the semiconductor layer; a step of forming a resist layer on the protection layer; a photolithography step of irradiating the resist layer with light through the metal layer to pattern the protection layer by photolithography technique; and a step of stacking a reflective layer on the patterned protection layer. A plurality of bumps are formed from the protection layer in the photolithography step, and a plurality of bumps corresponding to the plurality of bumps of the protection layer are formed on the reflective layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 28, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 8871640
    Abstract: A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kiyofumi Sakaguchi, Nobuo Kawase, Kenji Nakagawa
  • Patent number: 8872319
    Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Kim, Hee-Seok Lee, Seong-Ho Shin, Se-Ho You, Yun-Hee Lee
  • Patent number: 8866294
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8866302
    Abstract: A device includes a first semiconductor chip with a first contact pad on a first face and a second semiconductor chip with a first contact pad on a first face. The second semiconductor chip is placed over the first semiconductor chip, wherein the first face of the first semiconductor chip faces the first face of the second semiconductor chip. Exactly one layer of an electrically conductive material is arranged between the first semiconductor chip and the second semiconductor chip. The exactly one layer of an electrically conductive material electrically couples the first contact pad of the first semiconductor chip to the first contact pad of the second semiconductor chip.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
  • Patent number: 8865520
    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Pin Yang, Wei-Min Hsiao, Cheng-Hui Hung
  • Patent number: RE45286
    Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Olivier Le Neel, Peyman Sana, Loi Nguyen, Venkatesh Mohanakrishnaswamy