Mounting Semiconductor Bodies In Container (epo) Patents (Class 257/E21.5)
  • Patent number: 10058891
    Abstract: An ultrasound system (100) includes an ultrasound transducer array and a component (108) with electronics (110) embedded in a material (112) with at least one redistribution layer (114) electrically coupled to the embedded electronics, wherein the at least one redistribution layer electrically couples the ultrasound transducer array and the electronics.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: August 28, 2018
    Assignee: Sound Technology Inc.
    Inventors: Alessandro Gubbini, Bradley Nelson, Kristine Gamble
  • Patent number: 9991239
    Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Thorsten Meyer
  • Patent number: 9972601
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 15, 2018
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Patent number: 9818721
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 14, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 9799616
    Abstract: A package substrate has a sandwiched redistribution layers is disclosed. A middle redistribution layer functions as a core redistribution layer sandwiched by a top redistribution layer and a bottom redistribution layer. A top surface of the top redistribution layer is made adaptive for at least one chip to mount, and a bottom surface of the bottom redistribution layer is made adaptive for at least one chip to mount. A line width of each circuit of the middle redistribution layer is wider than a circuit of either the top redistribution layer or the bottom redistribution layer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 24, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9577067
    Abstract: Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Shuo Ho, Chang-Yin Chen, Chai-Wei Chang, Tsung-Yu Chiang
  • Patent number: 9524930
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Patent number: 8993376
    Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Patent number: 8890321
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao
  • Patent number: 8841159
    Abstract: A method for manufacturing an optoelectronic semiconductor component, comprising: providing a semiconductor chip in a composite wafer, comprising an active side for emitting a primary radiation and a contact terminal which is arranged on the active side; depositing a coupling element on the active side; attaching a luminescence conversion element, for converting part of the primary radiation into a secondary radiation, to the coupling element.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: September 23, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Hans-Christoph Gallmeier, Michael Kruppa, Raimund Schwarz, Guenter Spath
  • Patent number: 8809116
    Abstract: A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 19, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventor: Behnam Tabrizi
  • Patent number: 8779795
    Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 15, 2014
    Assignee: Renesas Elecronics Corporation
    Inventor: Yuta Takahashi
  • Patent number: 8736045
    Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: May 27, 2014
    Assignee: Raytheon Company
    Inventors: Roland Gooch, Buu Diep, Thomas Allan Kocian, Stephen H. Black, Allan M. Kennedy
  • Patent number: 8720049
    Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Tae Kyun Bae, Chang Gun Oh, Ho Sik Park
  • Patent number: 8709913
    Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 29, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 8703540
    Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Patent number: 8679900
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; mounting a lid base over the substrate, the lid base having a base indentation and a hole with the integrated circuit within the hole; and mounting a heat slug over the lid base, the heat slug having a slug non-horizontal side partially within the base indentation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, SangMi Park, MinJung Kim, MinWook Yu
  • Patent number: 8629001
    Abstract: A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Sugihara
  • Patent number: 8618619
    Abstract: A top port MEMS package includes a substrate and an interposer mounted to the substrate. The interposer includes an interposer aperture and an interposer channel fluidly coupled to the interposer aperture. A MEMS electronic component is mounted to the interposer above the interposer aperture. A top port lid includes a top port and a chimney structure fluidly coupling to the top port to the interposer channel. A front volume including the top port, the flue, the interposer channel, and the interposer aperture is acoustically sealed from a relatively large back volume defined by a lid cavity of the top port lid. By acoustically sealing the front volume from the back volume and further by maximizing the back volume, the noise to signal ratio is minimized thus maximizing the sensitivity of top port MEMS microphone package as well as the range of applications.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 31, 2013
    Inventors: Jeffrey Alan Miks, Louis B. Troche, Jr.
  • Publication number: 20130320516
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.
    Type: Application
    Filed: August 13, 2012
    Publication date: December 5, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Tae Sung Jeong, Yul Kyo Chung
  • Patent number: 8597984
    Abstract: A method of manufacturing a modular semiconductor subassembly: providing at least one semiconductor subassembly having a modular sidewall element of modular dimensions and a semiconductor substrate base element coupled to the modular sidewall element that has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element. If a modular package protective cover is to be used: providing the modular package protective cover configured to accommodate the semiconductor subassembly in accordance with a modular design; securing the semiconductor subassembly in the modular package protective cover to create a modular package assembly; and mounting the modular package assembly to a core, with a base side of the semiconductor substrate base element in contact with the core; otherwise: mounting the at semiconductor subassembly to the core, with the base side of the semiconductor substrate base element in contact with the core.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 3, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Craig J. Rotay
  • Patent number: 8592821
    Abstract: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic light-emitting transistor, a composite layer containing an organic compound having a hole-transporting property and a metal oxide is used as part of the electrode that injects holes among source and drain electrodes, and a composite layer containing an organic compound having an electron-transporting property and an alkaline metal or an alkaline earth metal is used as part of the electrode that injects electrons, where either composite layer has a structure of being in contact with an organic semiconductor layer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinobu Furukawa, Ryota Imahayashi
  • Publication number: 20130260511
    Abstract: A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies.
    Type: Application
    Filed: June 12, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang CHEN, Wei-Ting LIN, Yu-Chih LIU, Kuan-Lin HO, Jason SHEN
  • Patent number: 8546895
    Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 1, 2013
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Malta) Ltd
    Inventors: Mario Cortese, Mark Anthony Azzopardi, Edward Myers, Chantal Combi, Lorenzo Baldo
  • Publication number: 20130203199
    Abstract: A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Li-Cheng Chu, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Patent number: 8502252
    Abstract: An optoelectronic component (1) is provided, having at least two connecters (2) for electrical contacting of the component (1), a housing body (3), in which the connecters (2) are embedded in places, a heat sink (4), which is connected to at least one connecter (2), wherein the housing body (3) is formed of a plastics material, the housing body (3) comprises an opening (30), in which the heat sink (4) is freely accessible in places, at least one optoelectronic semiconductor chip (5) is arranged in the opening (30) on the heat sink (4), and at least two of the connecters (2) each comprise a chip-end portion (2c), which faces the at least one optoelectronic semiconductor chip (5), wherein the chip-end portions (2c) of the at least two connecters (2) are arranged in a common plane.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: August 6, 2013
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Stefan Groetsch, Thomas Zeiler, Michael Zitzlsperger, Harald Jaeger
  • Publication number: 20130194752
    Abstract: In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: Infineon Technologies AG
    Inventors: Carlo Baterna Marbella, Ganesh Vetrivel Periasamy, Kok Kiat Koo, Ai Min Tan
  • Patent number: 8497515
    Abstract: An improved light emitting diode (LED) device with a thermoelectric module is provided. In the preferred embodiment, the LED device herein includes a heat sink/housing containing a LED light, heat slug, and LED circuit board attached to a first side of a thermoelectric module and a heat sink on a second side of the thermoelectric module. Heat is conducted from the LED light and through the circuit board to the first side of the thermoelectric module. The heat sink housing dissipates heat from the second side of the thermoelectric module to create a temperature differential across the thermoelectric module and generate electricity.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 30, 2013
    Inventor: E. Mikhail Sagal
  • Patent number: 8497216
    Abstract: A method is described for manufacturing a micromechanical component. The method includes providing a first substrate, forming a first connecting structure on the first substrate, and forming a microstructure on the first substrate after forming the first connecting structure. The microstructure has at least one movable functional element. The method further includes providing a second substrate having a second connecting structure, and joining the first and second substrates by carrying out a bonding process, the first and second connecting structures being joined to form a common connecting structure, and a sealed cavity being formed in the region of the microstructure. The method provides that the first connecting structure takes the form of a buried connecting structure extending up to an upper surface of the first substrate. Also described is a related micromechanical component.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Mayer
  • Patent number: 8487443
    Abstract: Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 16, 2013
    Assignee: Teramikros, Inc.
    Inventor: Shinji Wakisaka
  • Patent number: 8486744
    Abstract: The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
  • Patent number: 8450216
    Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Publication number: 20130102112
    Abstract: A method includes loading a first package component on a concave boat, and placing a second package component over the first package component. A load clamp is placed over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat. A reflow step is performed to bond the second package component to the first package component. During a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Wei-Hung Lin, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8426253
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 23, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Publication number: 20130069218
    Abstract: The integrated circuit packaging techniques of the disclosed embodiments utilize a thermally conductive heat sink to partially enclose an integrated circuit. The heat sink is separated from the integrated circuit by a substrate that is conformally positioned into a recess in the heat sink, enabling the heat sink to transfer thermal energy from the integrated circuit.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: STMicroelectronics Asia Pacific Pte Ltd.
    Inventor: Lee Hua Alvin Seah
  • Publication number: 20130065364
    Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 14, 2013
    Applicant: RENESAS ELECTRIC CORPORATION
    Inventor: RENESAS ELECTRIC CORPORATION
  • Publication number: 20130062751
    Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.
    Type: Application
    Filed: April 26, 2011
    Publication date: March 14, 2013
    Inventors: Yusuke Takagi, Kaoru Uchiyama, Tokihito Suwa, Kinya Nakatsu, Takeshi Tokuyama, Shinji Hiramitsu
  • Patent number: 8394679
    Abstract: A structure and method for cold weld compression bonding using a metallic nano-structured gasket is provided. This structure and method allows a hermetic package to be formed at lower pressures and temperatures than are possible using bulk or conventional thin-film gasket materials.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 12, 2013
    Assignee: Stellarray, Inc.
    Inventors: Mark F Eaton, Curtis Nathan Potter, Andrew Miner
  • Publication number: 20130050228
    Abstract: This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, fabricating a glass package includes joining a cover glass panel to a glass substrate panel, and singulating the joined panels to form individual glass packages, each including one or more encapsulated devices and one or more signal transmission pathways. In another aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Kurt Edward Petersen, Ravindra V. Shenoy, Justin Phelps Black, David William Burns, Srinivasan Kodaganallur Ganapathi, Philip Jason Stephanou, Nicholas Ian Buchan
  • Patent number: 8367469
    Abstract: A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: February 5, 2013
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Patent number: 8334172
    Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: December 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
  • Publication number: 20120307541
    Abstract: This power converter includes a first substrate, a second substrate, a power conversion element, and a case portion, and the case portion includes a first connection terminal connected to a first conductor pattern arranged on a side of the first substrate closer to the power conversion element and a second connection terminal connected to a second conductor pattern arranged on a side of the second substrate opposite to the power conversion element.
    Type: Application
    Filed: February 20, 2012
    Publication date: December 6, 2012
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Shoichiro SHIMOIKE, Daisuke YOSHIMI
  • Patent number: 8324023
    Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 4, 2012
    Assignee: Atmel Corporation
    Inventor: Ken Lam
  • Patent number: 8314486
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: November 20, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HyungSang Park
  • Patent number: 8314484
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Publication number: 20120286413
    Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Frank Daeche
  • Patent number: 8309403
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 13, 2012
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Patent number: 8299589
    Abstract: A packaging device of an image sensor includes a supporting seat and the image sensor. The supporting seat is a hollow frame having a predetermined thickness, a first surface, a second surface, and an inner edge receding from the second surface toward the first surface to form a recessed step. Plural contacts in the recessed step and in the outer periphery of the supporting seat are electrically connected by plural electrical connection structures. The image sensor has an active surface set on the recessed step by a flip-chip packaging technique. The image sensor also has plural conductive ends electrically connected to the contacts in the recessed step. An insulating material covers an inactive surface of the image sensor and fills the gap between the recessed step of the supporting seat and the image sensor to provide dust-proofness, shock resistance, and prevention against static electricity and leakage of light.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: October 30, 2012
    Assignee: TDK Taiwan, Corp.
    Inventors: Wen Chang Lin, Chao Chang Hu, Zheng Hui Hsieh, Chih Jung Hung
  • Patent number: 8298862
    Abstract: A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: October 30, 2012
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Publication number: 20120237073
    Abstract: Microelectromechanical systems (MEMS) microphone devices and methods for packaging the same include a package substrate having an acoustic pathway therethrough that opens to an interior of the device. A MEMS microphone die having an integrated filter and a movable membrane is positioned within the interior of the device. The package substrate includes a conductive layer facing the interior of the device, and a package filter formed from the conductive layer is provided along the acoustic pathway, resulting in increased packaged MEMS microphone device yield.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Thomas Goida, Jicheng Yang, Woodrow Beckford