Attaching Or Detaching Leads Or Other Conductive Members, To Be Used For Carrying Current To Or From Device In Operation (epo) Patents (Class 257/E21.506)
  • Patent number: 8519534
    Abstract: At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 27, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, Eric Peeters
  • Publication number: 20130214419
    Abstract: A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Ming-Yi Liu
  • Publication number: 20130214431
    Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Kuei-Wei Huang, Ai-Tee Ang, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8513811
    Abstract: An electronic device including a die-pad area, a die fixed to the die-pad area, a connection terminal, and a ribbon of conductive material. The ribbon is electrically connected to the die and to the connection terminal, and has a prevalent dimension along a first axis, a width, measured along a second axis, which is transverse to the first axis, and a thickness, which is negligible with respect to the width; the ribbon moreover has a cross section that defines a concave geometrical shape.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 20, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Agatino Minotti, Giuseppe Cristaldi
  • Patent number: 8513108
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8513814
    Abstract: Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8507325
    Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 8508032
    Abstract: An electronic device package comprising: a block of insulating material; an electronic device housed within the insulating material and having a set of contact pads thereon; and a set of electrically conductive contact members at least partially housed within the insulating material, each contact member extending between a respective external contact point at which it is exposed at the surface of the block and an internal contact point from which it is electrically coupled to a respective contact pad on the electronic device, each internal contact point being outside the footprint of the electronic device, the set of contact members including: at least one contact member of a first type whose external contact point is located at least partially within the footprint of the electronic device; and at least one contact member of a second type that is wholly outside the footprint of the device.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: August 13, 2013
    Assignee: Cambridge Silicon Radio Limited
    Inventors: Martyn Robert Owen, Andrew George Holland
  • Patent number: 8501545
    Abstract: In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 6, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Grillberger, Matthias Lehr, Rainer Giedigkeit
  • Patent number: 8502363
    Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 6, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
  • Patent number: 8501547
    Abstract: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Robert J. Greenberg, Neil Hamilton Talbot, Jordan Matthew Neysmith, Jerry Ok, Honggang Jiang
  • Patent number: 8497160
    Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 30, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: François Hébert, Anup Bhalla, Kai Liu, Ming Sun
  • Patent number: 8497572
    Abstract: In a semiconductor module, a first heat sink is disposed on a rear surface of a first semiconductor chip constituting an upper arm, and a second heat sink is disposed on a front surface of the first semiconductor chip through a first terminal. A third heat sink is disposed on a rear surface of a second semiconductor chip constituting a lower arm, and a fourth heat sink is disposed on a front surface of the second semiconductor chip through a second terminal. A connecting part for connecting between the upper arm and the lower arm is integral with the first terminal, and is connected to the third heat sink while being inclined relative to the first terminal.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 30, 2013
    Assignee: DENSO CORPORATION
    Inventors: Keita Fukutani, Kuniaki Mamitsu, Yasushi Ookura, Masayoshi Nishihata, Hiroyuki Wado, Syun Sugiura
  • Publication number: 20130187259
    Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 8492883
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 23, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Chien-Wen Chen, Hsu-Yang Lee
  • Patent number: 8492887
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jayby Agno, Erwin Aguas Sangalang, Dexter Anonuevo, Ramona Damalerio
  • Publication number: 20130181304
    Abstract: Methods and apparatus to provide an integrated circuit package having a conductive leadframe, a non-conductive die paddle mechanically coupled to the leadframe, and a die disposed on the die paddle and electrically connected to the leadframe. With this arrangement, eddy currents are reduced near the magnetic field transducer to reduce interference with magnetic fields.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: ALLEGRO MICROSYSTEMS, INC.
    Inventors: Shaun D. Milano, Michael C. Doogue, William P. Taylor
  • Publication number: 20130183823
    Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Hua-An Dai, Cheng-Fan Lin, Yie-Chuan Chiu, Yung-Wei Hsieh
  • Patent number: 8487431
    Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sin-Hyun Jin, Jong-Chern Lee
  • Patent number: 8486766
    Abstract: The invention relates to thermally contacting a semiconductor component arrangement, wherein at least one of two heat conducting bodies disposed on opposite sides of the semiconductor component arrangement is brought into contact with a contact surface of the semiconductor component arrangement by means of a metal layer under the application of a force, wherein the metal layer melts during solidification of a locking agent, forming an adhesive bond between the two heat transfer bodies over the entire region thereof.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: July 16, 2013
    Assignee: JENOPTIK Laser GmbH
    Inventors: Matthias Schroeder, Dominic Schroeder, Petra Hennig
  • Publication number: 20130175704
    Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: IXYS Corporation
    Inventors: Gi-Young Jeun, Kang Rim Choi
  • Patent number: 8482118
    Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: July 9, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Anuraag Mohan, Peter Smeys
  • Publication number: 20130168848
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
  • Publication number: 20130168857
    Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 4, 2013
    Inventors: Thomas Matthew GREGORICH, Andrew C. CHANG, Tzu-Hung LIN
  • Patent number: 8476720
    Abstract: A sensing unit package with reduced size and improved thermal sensing capabilities. An exemplary package includes a printed circuit board with a plurality of electrical traces, an application-specific integrated circuit (Analog ASIC) chip, and a micromachined sensor formed on a microelectromechanical system (MEMS) die. The Analog ASIC chip is electrically and mechanically attached to the printed circuit board. The MEMS die is in direct electrical communication with only a portion of the electrical traces of the printed circuit board and is mechanically and thermally attached directly to the Analog ASIC chip. A thermally conducting compound is located between the MEMS die and the Analog ASIC chip. One or more solder balls electrically attach the Analog ASIC chip to the printed circuit board and one or more solder traces electrically attach the MEMS die to the printed circuit board.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventor: Chia-Ming Liu
  • Patent number: 8471373
    Abstract: A resin-sealed semiconductor device includes a power element (1), a control element (4), a first lead frame (3) having a first die pad (3A) which holds the power element (1), a second lead frame (5) having a second die pad (5A) which holds the control element (4), and a housing (6) made of a resin material and sealing the power element, the first die pad, the control element, and the second die pad. A lower surface of the second die pad is higher than an upper surface of the first element, and at least part of the first die pad and at least part of the second die pad overlap each other when viewed from the top. One of the first leads and one of the second leads are directly joined together by a joint portion (23) and electrically coupled together in the housing.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Shinichi Ijima
  • Publication number: 20130154118
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154072
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154080
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8466545
    Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 18, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Akito Yoshida, Young Wook Heo
  • Publication number: 20130146991
    Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Joachim Mahler, Johannes Lodermeyer
  • Publication number: 20130147032
    Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu JENG, Wei-Cheng WU, Shang-Yun HOU, Chen-Hua YU, Tzuan-Horng LIU, Tzu-Wei CHIU, Kuo-Ching HSU
  • Publication number: 20130147041
    Abstract: A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls.
    Type: Application
    Filed: August 13, 2012
    Publication date: June 13, 2013
    Applicant: Unimicron Technology Corporation
    Inventors: Ying-Chih CHAN, Jiun-Ting LIN
  • Patent number: 8455303
    Abstract: This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: June 4, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaotian Zhang, Jun Lu
  • Publication number: 20130134602
    Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Invensas Corporation
    Inventors: Kazuo Sakuma, Ilyas Mohammed, Philip Damberg
  • Patent number: 8450837
    Abstract: In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 28, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Shigeki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
  • Publication number: 20130127008
    Abstract: In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Luu T. Nguyen
  • Patent number: 8445375
    Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an opening. Then, a larger portion of the photoresist layer is exposed to light and an electrically conductive interconnect is formed in the opening. The larger portion of the photoresist layer that was exposed to light is developed to expose edges of the electrically conductive interconnect and portions of the metallization structure. A protection layer is formed on the top and edges of the electrically conductive interconnect and on the exposed portions of the metallization structure.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 21, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Publication number: 20130120951
    Abstract: A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
    Type: Application
    Filed: January 24, 2012
    Publication date: May 16, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Changhan Yun, Sang-June Park, Chi Shun Lo, Mario F. Velez, Jonghae Kim
  • Patent number: 8440506
    Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan
  • Publication number: 20130113093
    Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.
    Type: Application
    Filed: October 7, 2011
    Publication date: May 9, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Nazir Ahmad, Young-Do Kweon, Samuel Tam, Kyung-Moon Kim, Rajendra D. Pendse
  • Publication number: 20130109136
    Abstract: In an embodiment of the present invention, a method is provided for fabricating an electronics assembly having a substrate and a plurality of circuit elements. The method includes forming a liquid barrier on the substrate, placing a first circuit element on one side of the liquid barrier, and placing a second circuit element on the opposite side of the liquid barrier. A liquid is applied to the first circuit element.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: NORDSON CORPORATION
    Inventors: David K. Foote, James D. Getty, Jiangang Zhao
  • Publication number: 20130109137
    Abstract: A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.
    Type: Application
    Filed: May 25, 2012
    Publication date: May 2, 2013
    Applicant: CARSEM (M) SDN. BHD
    Inventors: Yong Lam Wai, Chan Boon Meng, Phang Hon Keat
  • Patent number: 8431436
    Abstract: At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventor: Son V. Nguyen
  • Publication number: 20130099367
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.
    Type: Application
    Filed: June 19, 2012
    Publication date: April 25, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Emmanuel Espiritu
  • Patent number: 8426742
    Abstract: The connection reliability of connecting terminals with displacement gold plating films is improved by connecting terminals comprising a conductive layer, an electroless nickel plating film, a first palladium plating film which is a displacement or electroless palladium plating film with a purity of 99% by mass or greater, a second palladium plating film which is an electroless palladium plating film with a purity of at least 90% by mass and less than 99% by mass, and a displacement gold plating film, wherein the electroless nickel plating film, the first palladium plating film, the second palladium plating film and the displacement gold plating film are laminated in that order on one side of the conductive layer, and the displacement gold plating film is situated on the uppermost surface layer on the opposite side from the conductive layer.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: April 23, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshinori Ejiri, Shuichi Hatakeyama, Shigeharu Arike, Kiyoshi Hasegawa
  • Publication number: 20130095610
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 18, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 8420430
    Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
  • Patent number: 8421219
    Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi So, Hideo Kubo, Seiji Ueno, Osamu Igawa
  • Publication number: 20130087914
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG