Right-up Bonding (epo) Patents (Class 257/E21.512)
  • Patent number: 7282395
    Abstract: A method of making an exposed-pad ball-grid array package (11) includes applying a conductive sheet (16) to an adhesive tape (18). Stamping the conductive sheet (16) to form a die pad (24) and separating the remainder (26) of the sheet from the adhesive tape (18) so that only the die pad (24) remains on the adhesive tape (18). A substrate (28) is applied to the adhesive tape (18) proximate to the die pad (24). A die (30) is attached to the die pad (24) and electrically coupled to the substrate (28). An encapsulant (34) is formed around at least a portion of the die (30), the die pad (24) and the substrate (28) above the adhesive tape (18). The adhesive tape (18) is removed from the die pad (24), substrate (28) and encapsulant (34). Conductive balls (36) are attached to the substrate (28).
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: October 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Heng Keong Yip
  • Patent number: 7256496
    Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: August 14, 2007
    Assignee: Casio Computer Co., Ltd.
    Inventors: Osamu Okada, Hiroyasu Jobetto
  • Patent number: 7244635
    Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 17, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 7199459
    Abstract: A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respectively, two conductive trace layers formed on the dielectric layers respectively, an insulating layer formed on one of the dielectric layers, and a plurality of solder balls implanted on the back surface of the substrate. One of the dielectric layers is formed on one of the chips and attached to an entire non-active surface of the other of the chips.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: April 3, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Han-Ping Pu, Chien Ping Huang