Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS device by using metal thermocompression bonding to assemble a reference wafer (100), a bulk MEMS active wafer (200), and a cap wafer (300) to provide a proof mass (200d) formed from the active wafer with bottom and top capacitive sensing electrodes (115, 315) which are hermetically sealed from the ambient environment by sealing ring structures (112/202/200a/212/312 and 116/206/200e/216/316).

Abstract: A semiconductor device includes a die pad having a surface on which a first solder bonding layer is formed, and made of metal; and a semiconductor element fixed on the first solder bonding layer on the die pad by a solder material made mostly of bismuth. The first solder bonding layer is made of a softer material than the solder material, a recess is formed in a part of the first solder bonding layer by pressing the solder material against the first solder bonding layer, and the solder material partially fills the recess.

Abstract: A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.

Abstract: An electrical generator includes a substrate, a semiconductor piezoelectric structure having a first end and an opposite second end disposed adjacent to the substrate, a first conductive contact and a second conductive contact. The structure bends when a force is applied adjacent to the first end, thereby causing an electrical potential difference to exist between a first side and a second side of the structure. The first conductive contact is in electrical communication with the first end and includes a material that creates a Schottky barrier between a portion of the first end of the structure and the first conductive contact. The first conductive contact is also disposed relative to the structure in a position so that the Schottky barrier is forward biased when the structure is deformed, thereby allowing current to flow from the first conductive contact into the first end.

Abstract: Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can be formed on each I/O bond-pad on the chip. The chip is flipped and placed on the stud-bumps such that the I/O bond-pads on the chip are registered with the corresponding stud-bumps on the substrate. At each stud-bump, the fusible material is caused to fuse with and electrically connect the respective stud-bump to the respective I/O bond-pad on the chip. The method can include forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip before placing the chip on the stud-bumps. The resulting structures provide robust I/O connections and can be fabricated using fewer process steps and using process steps that are compatible with other processes in wafer-fabrication and chip-assembly facilities.

Abstract: A power semiconductor module in a pressure contact embodiment and a method for producing such modules, for disposition on a cooling component. Load terminals of the modules are formed as metal molded bodies having at least one contact element, one flat portion, and contact feet emanating therefrom. Each flat portion is disposed parallel to, and spaced from, the surface of the substrate. The contact feet extend from the flat portion to the substrate. An elastic intermediate layer is disposed between adjacent load terminals, in the region of the respective flat portions, and the intermediate layer and load terminals form a stack.

Abstract: A recess portion is formed on a board surface at a position facing a peripheral end portion of a semiconductor device so as to place a sealing-bonding use resin partially inside the recess portion. Thereby, increases of a placement area for a fillet portion (foot spreading portion) of the sealing-bonding use resin are suppressed while its inclination angle is increased. Thus, stress loads that occur to peripheral portions of the semiconductor device due to thermal expansion differences and thermal contraction differences among individual members caused by heating process and cooling process in mounting operation are relaxed, by which internal breakdown of the semiconductor device mounted structure is avoided.

Abstract: A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

Abstract: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Abstract: A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set.

Abstract: The invention relates to a method of bonding a polymer surface to an electrically conductive or semiconductive surface, which method is characterized in that it comprises: a) the electrografting of an organic film onto the conductive or semiconductive surface; and then b) an operation of bonding the polymer surface to the conductive or semiconductive surface thus grafted. It also relates to applications of this method and to structures obtained by its implementation.

Abstract: A method for forming an internal electrode pattern having a predetermined shape includes the following: a step of forming a conductive layer by applying a metal paste on a first support, the metal paste containing metal powder and a binder; a step of forming a resin layer on a second support, the resin layer having a pattern negative to the internal electrode pattern; a step of compression bonding the first support and the second support to each other in such a manner that the conductive layer and the resin layer are opposite to each other; and a step of removing the second support from the first support so as to transfer a conductive layer to the second support, the conductive layer having the pattern negative to the internal electrode pattern, thereby forming the internal electrode pattern having the predetermined shape on the first support.

Abstract: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.

Abstract: A method for assembling a semiconductor device including the steps of providing a penetrable substrate having an adhesive surface and a plurality of dies disposed on the adhesive surface; providing a strap lead substrate having a plurality of strap leads disposed thereon; dispensing a first plurality of strap leads from the plurality of strap leads; providing a plurality of pins; bringing the penetrable substrate into close proximity with the strap lead substrate so as to bringing the first plurality of strap leads into contact with the plurality of dies; pressing the first plurality of strap leads against the plurality of dies using the plurality of pins; and, moving the penetrable substrate away from the strap lead substrate while using the plurality of pins to maintain contact between the first plurality of strap leads and the plurality of dies. An apparatus for assembling a semiconductor device is also disclosed.

Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

Abstract: The present invention relates to a method of manufacturing a resonator within a semiconductor device, said semiconductor device comprising a substrate, wherein said method comprises the steps of: etching a hole in the substrate, creating a first doping zone (Z-DIFF1) for defining a first electrode, partitioning said first electrode into two electrodes, applying a delimited oxide deposit inside and around the hole, defining a second doping zone (Z-DIFF2) totally covering the hole, removing the oxide deposit in order to define an element forming the resonator able to vibrate between the two electrodes.

Abstract: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows a Micro-Electro-Mechanical Systems device or semiconductor to be subjected to temperatures above 385° C. without risking gold diffusion. Removing the risk of gold diffusion allows further elevated temperature processing. Bonding a device substrate to a carrier substrate can be an elevated temperature process.

Abstract: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 ?m or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Abstract: A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region, and has a surface configuration including raised parts. A first dummy pattern is formed in a region between the peripheral ring electrode and the device element on the substrate.

Abstract: An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. The grooves in the capping layer may be located only proximate to the edges of the bond pad or may run throughout the bond pad depending on the application.

Abstract: A hermetic seal cover capable of inhibiting defects such as voids from generating in sealing a package, and a method of manufacturing the seal cover are provided. The hermetic seal cover comprises: a seal cover main body; a Ni plating layer applied onto a surface of the seal cover main body; and a Au—Sn brazing material layer fusion bonded to a surface of the Ni plating layer, and is characterized by a Ni—Sn ally layer disposed between the Ni plating layer and the Au—Sn brazing material layer. It is preferable if the Ni—Sn alloy layer has a thickness of 0.6-5.0 ?m. It is also preferable if Au—Sn brazing material layer has a Sn content of 20.65-23.5 wt %.

Abstract: A method is provided for producing a smart card comprising a chip module with at least one contacting area, the chip module arrangeable in a mounting location of a substrate, wherein one contacting loop is formed from a wire connector fed by a wire guiding unit for at least one of the contacting areas, respectively by attaching a first section of the wire conductor to a surface of the substrate outside the mounting location, wherein a second section of the wire conductor proximate to the first section is guided to form the contacting loop along with and protruding from the surface, wherein a subsequent third section of the wire conductor is attached to the surface outside the mounting location, wherein the chip module is inserted into the mounting location and wherein the second section is bent over and electrically contacted to the contacting area.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: A method of manufacturing a radiating plate using In as a thermal conducting bonding material 20 provided between a semiconductor device and a radiating plate 14 and serving to bond a back surface of the semiconductor device to the radiating plate, includes the steps of carrying out a cleaning treatment for cleaning a surface of the radiating plate 14, supplying the In to the radiating plate 14, heating and melting the In and hermetically adhering the In 18 to the radiating plate, thereby obtaining an In integral type radiating plate.

Abstract: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature.

Abstract: A process of making an integrated heat spreader is disclosed. The integrated heat spreader is stamped with a thermal interface material under conditions to form a diffusion bonding zone between the integrated heat spreader and the thermal interface material. The thermal interface material can have one of several cross-sectional profiles to facilitate reflow thereof against a die during a method of assembling a packaged microelectronic device. The thermal interface material can also have one of several footprints to further facilitate reflow thereof against the die.

Abstract: A semiconductor device includes a semiconductor chip mounted on a printed circuit board with a chip electrode being coupled to a board electrode via a bump electrode. An insulating resin layer including therein conductive particles is interposed between the bump electrode and each of the chip electrode and board electrode. The conductive particles couple together the bump electrode and the each of the chip electrode and the board electrode. The conductive particles and the bump electrode are deformed to have a flat shape due the stress applied between the semiconductor chip and the printed circuit board.

Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.

Abstract: A semiconductor chip is attached to a lead frame with a filmy organic die-bonding material having a water absorption of 1.5% by volume or less; having a saturation moisture absorption of 1.0% by volume or less, having a residual volatile component in an amount not more than 3.0% by weight, having a modulus of elasticity of 10 MPa or less at a temperature of 250° C. The semiconductor device thus obtained can be free from occurrence of reflow cracks during reflow soldering for the packaging of semiconductor devices.

Abstract: A semiconductor device comprises a semiconductor element having electrodes, a metal member, wires that electrically connect the semiconductor element and the metal member and/or electrodes within the semiconductor element, wherein the wires constitute at least a first wire loop and a second wire loop, the first wire loop is bonded at one end to a first bonding point and at the other end to a second bonding point, and has a flat part which includes the surface of a boll part and the wire located contiguously the ball part surface, and the second wire loop connects the surface of the ball part and a third bonding point.

Abstract: A wafer bonding method, comprising steps of: coating a medium layer respectively on the surfaces of two wafers; removing impurities formed on the surface of each medium layer; laminating the two wafers while enabling the surface coated with the medium layer of one of the two wafers to face the surface coated with the medium layer of another wafer; and applying an ultra-sonic oscillation and a bonding pressure upon the laminated wafers for bonding the two wafers.

Abstract: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is simultaneously folded under the package base to supply force maintenance for permanent hermaticity. The swage hermetic sealing of single or an array of covers to an extended wafer or substrate is accomplished by a cutting and flowing edge 560. Permanent force maintenance is achieved through a re-entrant cavity 565 and annular ring 535 on the wafer or substrate.

Abstract: A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so as to have a shape in which is formed a region for receiving a soldering or brazing material.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: A wiring pattern is provided on an insulating tape. Part of the wiring pattern is a connection section. An insulating resin is provided so that the connection section is coated with the insulating resin. A protrusion electrode of a semiconductor element is so positioned on the connection section so that the protrusion electrode will push away the insulating resin and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. Heat is applied while pressing in Direction D1. In this way, the connection section intrudes into the protrusion electrode, thereby causing the connection section and the protrusion electrode to be connected with each other.

Abstract: A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, and sealing resin which covers the circuit elements. The circuit device has a structure in which Pb-free solder containing Bi is used as the bonding material. Since the melting temperature of Bi is high in comparison with that of a general solder, the melting of the bonding material is suppressed when the circuit device is mounted. Further, Ag or the like may be mixed into the bonding material in order to enhance the wettability of the bonding material.

Abstract: A method of manufacturing a semiconductor device is provided including depressing a bonding tool having a concave portion toward a wiring board with a semiconductor chip disposed within the concave portion, pressing the semiconductor chip with a bottom face of the concave portion, fluidizing a resin provided between the semiconductor chip and the wiring board, and filling a lateral space proximate the semiconductor chip within the concave portion with the resin, and curing the resin.

Abstract: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one another is formed on a semiconductor element, an end portion of the metal wire is connected to an electrode on the semiconductor element, the other end portion of the metal wire is connected to an external terminal to form a land, the entire surface of the semiconductor element except the connecting portions of the lands is covered with a surface-layer resin layer, and a projection is provided on the top surface of a land portion of at least one of the lands. Because of this, after their soldering, the external terminal holds the perimeter of the projection on the land portion, so that the external terminal can be surely connected to the land portion.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract: A device for assembling circuit boards. The device has an upper surface for receiving a compressing force. The device also has a lower surface for compressing a number of compression devices in a land grid array assembly while allowing access to a number of fasteners associated with the compression devices. The device is able to assist in the formation of an electrical contact between a chip package in the land grid array assembly and a circuit board by the lower surface being pressed against the compression devices to compress the compression devices and then allowing the plurality of fasteners to be tightened.