Testing Or Measuring During Manufacture Or Treatment Or Reliability Measurement, I.e., Testing Of Parts Followed By No Processing Which Modifies Parts As Such (epo) Patents (Class 257/E21.521)

  • Patent number: 8241928
    Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 14, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chao-I Wu, Ming-Chang Kuo
  • Patent number: 8236587
    Abstract: Disclosed is a robot for transferring a substrate, wherein the robot has a robot arm, a hand part, which includes a plurality of plates. A plurality of pins protrude from the plates such that each pin may be folded downward. The pins include a rubber or resin with thermally insulating properties. By selectively folding down a certain number of the pins, contact may be minimized between the substrate and the robot, thereby preventing damage to the substrate such as thermally-induced defects and stains.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: August 7, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Deuk Soo Kim
  • Patent number: 8237160
    Abstract: A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Chung-Ying Yang, Ying-Ju Chen, Shih-Wei Liang, Ching-Jung Yang
  • Patent number: 8237278
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Publication number: 20120196388
    Abstract: An object is to provide a method for manufacturing a light-emitting device in which a defective portion is insulated. In addition, another object is to provide a manufacturing apparatus of a light-emitting device in which a defective portion is insulated. After a hemispherical lens is formed to overlap with a light-emitting element, the defective portion is detected. Then, the hemispherical lens overlapping with the light-emitting element including the detected defective portion may be irradiated with a laser beam having a low energy density, and the defective portion may be insulated by light condensed through the hemispherical lens.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Koichiro TANAKA
  • Patent number: 8232113
    Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: July 31, 2012
    Assignee: STMicroelectronics (Grenoble) SAS
    Inventor: Romain Coffy
  • Publication number: 20120187494
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Publication number: 20120190136
    Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 26, 2012
    Applicant: Protec Co., Ltd.
    Inventor: Seung Min Hong
  • Publication number: 20120190133
    Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, JR., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Publication number: 20120181678
    Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: NXP B.V.
    Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
  • Publication number: 20120182816
    Abstract: Such a device is disclosed that includes: a row redundancy circuit and a column redundancy circuit for replacing defective sub word lines and defective bit lines included in a memory cell array, respectively; first and second electrical fuse circuits that store the addresses of the defective sub word lines and the defective bit lines, respectively; and a fuse select circuit that selects, in a first operation mode, either one of the first and second electrical fuse circuits based on an address signal supplied when a determination signal is activated, and selects, in a second operation mode, the other of the first and second electrical fuse circuits based on the address signal supplied when the determination signal is activated. According to the present invention, it is possible to flexibly switch between replacement using redundant word lines and replacement using redundant bit lines.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Inventors: Akira Ide, Hiroki Ichikawa
  • Publication number: 20120175780
    Abstract: One embodiment provides a semiconductor chip including a semiconductor body and a power semiconductor component integrated therein. The power semiconductor component includes a load electrode zone arranged on a first surface of the semiconductor body, a control electrode zone arranged on the first surface, the control electrode zone being electrically insulated from the load electrode zone, and a resistance track arranged on the load electrode zone and the control electrode zone. The resistance track ensures an electrical connection between the load electrode zone and the control electrode zone.
    Type: Application
    Filed: March 19, 2012
    Publication date: July 12, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Patrick Baginski, Reinhold Bayerer, Holger Ruething, Daniel Domes
  • Patent number: 8216927
    Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: July 10, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Ralf Richter, Frank Feustel, Thomas Werner, Kai Frohberg
  • Publication number: 20120167948
    Abstract: A method for forming a solar energy collection device includes determining physical concentration characteristics for a plurality of light concentrating geometric features of a sheet of transparent material, determining placements for a plurality of photovoltaic strips in response to the physical concentration characteristics for the plurality of light concentrating geometric features, wherein the placements for each of the plurality of photovoltaic strips is associated with a two-dimensional displacement and an offset angle, placing the plurality of photovoltaic strips onto a stage in response to two-dimensional displacements and offset angles associated with each of the plurality of photovoltaic strips, and electrically coupling the plurality of photovoltaic strips with a plurality of conductors to form a photovoltaic assembly.
    Type: Application
    Filed: December 31, 2010
    Publication date: July 5, 2012
    Applicant: Solaria Corporation
    Inventors: Ajay Marathe, Douglas R. Battaglia, JR., Frank Magana, Raghunandan Chaware
  • Publication number: 20120167947
    Abstract: A method for forming a solar energy collection device includes receiving a first photovoltaic string comprising a first plurality of photovoltaic strips coupled via a first plurality of conductors, wherein the first photovoltaic string is tested to have a first dark-field current/voltage characteristic, receiving a second photovoltaic string comprising a second plurality of photovoltaic strips coupled via a second plurality of conductors, wherein the second photovoltaic string is tested to have a second dark-field current/voltage characteristic, electrically coupling the first photovoltaic string and the second photovoltaic string, and wherein the first dark-field current/voltage characteristic is substantially similar to the second dark-field current/voltage characteristic.
    Type: Application
    Filed: December 31, 2010
    Publication date: July 5, 2012
    Applicant: Solaria Corporation
    Inventors: Douglas R. BATTAGLIA, JR., Qi Zhang
  • Patent number: 8211720
    Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Fischer, Alexander Von Glasow, Jochen Von Hagen
  • Patent number: 8206997
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Patent number: 8203192
    Abstract: Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 19, 2012
    Assignee: Seagate Technology LLC
    Inventors: Kaizhong Gao, Haiwen Xi, Wenzhong Zhu, Olle Heinonen
  • Publication number: 20120149134
    Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.
    Type: Application
    Filed: November 8, 2011
    Publication date: June 14, 2012
    Applicant: Advanced Inquiry Systems, Inc.
    Inventor: Morgan T. Johnson
  • Patent number: 8198627
    Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woo-seop Jeong
  • Publication number: 20120142123
    Abstract: A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs etching to form device waveguides and mirrors, preferably using a temperature of over 500° C. and an ion beam in excess of 500 V in CAIBE.
    Type: Application
    Filed: February 15, 2012
    Publication date: June 7, 2012
    Inventors: ALEX A. BEHFAR, Alfred T. Schremer, Cristian B. Stagarescu, Vainateya
  • Publication number: 20120138925
    Abstract: A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.
    Type: Application
    Filed: November 30, 2011
    Publication date: June 7, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Tac Keun OH
  • Patent number: 8193007
    Abstract: Provided is a method and system for controlling a fabrication cluster for processing of a substrate in an etch process, the fabrication cluster having equipment settings and process parameters. A correlation of etch stage measurements to actual etch stage data is developed, the etch stage measurements comprising measurements using two or more optical metrology devices and an etch sensor device. An etch stage value is extracted using the developed correlation and the etch stage measurement. If the etch stage measurement objectives are not met, the metrology devices are modified, a different etch sensor device is selected, the etch stage measurements are enhanced, and/or the correlation algorithm is refined. The steps are iterated until the etch stage measurement objectives are met. The extracted etch stage value is used to adjust an equipment setting and/or process parameter of the fabrication cluster.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: June 5, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Manuel Madriaga, Xinkang Tian
  • Publication number: 20120135548
    Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
    Type: Application
    Filed: February 5, 2012
    Publication date: May 31, 2012
    Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
  • Publication number: 20120126230
    Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 24, 2012
    Applicant: STMicroelectronics SA
    Inventors: Richard Fournel, Pierre Dautriche
  • Publication number: 20120119778
    Abstract: A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ishtiaq Ahsan, David M. Fried, Lidor Goren, Jiun-Hsin Liao
  • Publication number: 20120121061
    Abstract: A shift register according to the present invention is supported on an insulating substrate and has multiple stages that sequentially shift an output signal from one stage to the next. Each of those stages has a circuit 20 including multiple thin-film transistors. The multiple thin-film transistors include a first thin-film transistor MK, which influences the operation of the circuit, and a second thin-film transistor MK_YOBI, which has at least one floating terminal and other terminal(s) that is/are connected to corresponding terminal(s) of the first thin-film transistor MK. The at least one floating terminal is arranged so as to be connectible to a predetermined line N2. Consequently, the yield of shift registers with a monolithic gate driver can be increased.
    Type: Application
    Filed: February 1, 2010
    Publication date: May 17, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Mayuko Sakamoto, Yasuaki Iwase
  • Publication number: 20120122253
    Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.
    Type: Application
    Filed: January 4, 2012
    Publication date: May 17, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Blake Koelmel, Abhilash J. Mayur, Kai Ma, Alexander N. Lerner
  • Patent number: 8178876
    Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: May 15, 2012
    Assignee: PDF Solutions, Inc.
    Inventors: Christopher Hess, David Goldman
  • Publication number: 20120112338
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 10, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Patent number: 8173451
    Abstract: Provided is a system for measuring an etch stage of an etch process involving one or more layers in a substrate, the etch stage measurement system configured to meet two or more etch stage measurement objectives. The system includes an etch process tool, the etch process tool having an etch chamber, a controller, and process parameters. The etch process tool is coupled to two or more optical metrology devices and at least one etch sensor device measuring an etch process parameter with high correlation to the etch stage. The processor is coupled to the etch process tool and is configured to extract an etch measurement value using a correlation of etch stage measurements to actual etch stage data and etch stage measurement obtained from the two or more metrology devices and the at least one etch process sensor device.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: May 8, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Xinkang Tian, Manuel Madriaga
  • Patent number: 8173450
    Abstract: Provided is a method for designing an etch stage measurement system involving an etch process for one or more layers on a substrate using an etch process tool. The etch process tool uses two or more metrology devices, at least one etch process sensor device, and a metrology processor, the etch stage measurement system configured to meet two or more etch stage measurement objectives. A correlation algorithm using the etch stage measurements to the actual etch stage data is developed and used to extract etch measurement value. If the set two or more etch stage measurement objectives are not met, the optical metrology devices are modified, a different etch process sensor device is selected, the correlation algorithm is refined, and/or the measurement data is enhanced by adjusting for noise.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 8, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Xinkang Tian, Manuel Madriaga
  • Publication number: 20120107971
    Abstract: A polishing pad assembly for a chemical mechanical polishing apparatus includes a polishing pad having a polishing surface and a surface opposite the polishing surface for attachment to a platen, and a solid light-transmissive window formed in the polishing pad. The light-transmissive window is more transmissive to light than the polishing pad. The light-transmissive window has a light-diffusing bottom surface.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Inventors: Manoocher Birang, Grigory Pyatigorsky
  • Publication number: 20120105093
    Abstract: A semiconductor apparatus includes: a semiconductor chip, wherein a conductive layer is formed at one side of the semiconductor chip and one or more of probe pads are formed at the other side thereof; a plurality of through-silicon vias (TSVs), wherein one side of each of the plurality of TSVs is coupled to the conductive layer and the other side of one or more of the plurality of TSVs is coupled to the probe pad; a plurality of latch units each configured to be assigned to the plurality of corresponding TSVs and store a test signal, wherein the test signal is inputted via the probe pad and is transferred via the plurality of corresponding TSVs to the plurality of assigned latch units, respectively; and a signal combination unit configured to combine a plurality of signals stored in the plurality of latch units to output the result as an error detection signal.
    Type: Application
    Filed: December 30, 2010
    Publication date: May 3, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Tae Yong LEE
  • Publication number: 20120100641
    Abstract: According to an embodiment, an etching apparatus includes a reaction chamber, a vacuum pump connected to the reaction chamber through the gate valve, a holding unit which holds a processing subject, an etching gas supply unit, a heating unit, and a sublimation amount determining unit. The etching gas supply unit supplies an etching gas which forms a reaction product by reacting with the processing subject to the reaction chamber. The heating unit heats the processing subject to an equal or higher temperature than temperature at which the reaction product will be sublimated. The sublimation amount determining unit monitors a predetermined physical amount which changes depending on the degree of sublimation of the reaction product during the sublimation process using the heating unit, in which the physical amount is used as a sublimation-amount-dependent change value which changes over time.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhiko TACHIBANA, Kenta Yoshinaga
  • Patent number: 8163573
    Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Shunji Yoshida, Ryou Kato, Toshiya Yokogawa
  • Publication number: 20120091421
    Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.
    Type: Application
    Filed: June 30, 2010
    Publication date: April 19, 2012
    Inventors: Dianzhong Wen, Xiaohui Bai
  • Publication number: 20120088316
    Abstract: In a system or method for controlling wafer back-grinding, a chuck table has a surface for supporting a semiconductor wafer during a back-grinding process, one or more holes in the surface, and one or more sensors disposed in the one or more holes for monitoring a parameter during back-grinding. A computer-implemented process control tool is coupled to receive one or mote outputs from the one or more sensors and control the back-grinding process based on the received one or more outputs.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Fa LU, Chiang-Hao LEE, Wei-Yu CHEN, Chung-Shi LIU
  • Publication number: 20120074537
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Sung Mun JUNG, Swee Tuck WOO, Sanford CHU, Liang Choo HSIA
  • Publication number: 20120077290
    Abstract: An aspect of the present invention relates to a method of etching a surface layer portion of a silicon wafer comprising: positioning the silicon wafer within a sealed vessel containing a mixed acid A of hydrofluoric acid and sulfuric acid so that the silicon wafer is not in contact with mixed acid A; introducing a solution B in the form of nitric acid containing nitrogen oxides into the sealed vessel and causing solution B to mix with mixed acid A; and vapor phase decomposing the surface layer portion of the silicon wafer within the sealed vessel within which mixed acid A and solution B have been mixed.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 29, 2012
    Applicant: SUMCO CORPORATION
    Inventors: Jiahong WU, Shabani B. MOHAMMAD
  • Publication number: 20120069632
    Abstract: Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0<x?0.85) added with hydrogen or fluorine. When D (D=D0×1022 atoms/cm3) represents a density of hydrogen or fluorine, d (nm) represents a thickness of the current steering layer (33), and V0 (V) represents a maximum value applicable to between the first electrode (32) and the second electrode (31), D, x, d, and V0 satisfy the following Formulae. (ln(10000(C·exp(?·d)exp(?·x))?1)?)2?V0 (ln(1000(C·exp(?·d)exp(?·x))?1)?)2?(ln(10000(C·exp(?·d)exp(?·x))?1)?)2/2?0 wherein C=k1×D0k2, and ?, ?, ?, k1, and k2 are constants.
    Type: Application
    Filed: March 10, 2011
    Publication date: March 22, 2012
    Inventors: Yukio Hayakawa, Koji Arita, Takumi Mikawa, Takeki Ninomiya
  • Publication number: 20120068175
    Abstract: A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ryan D. Lane, Ruey Kae Zang
  • Publication number: 20120068176
    Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, an edge seal, a plurality of pad pieces, and an insulating film pattern. The semiconductor substrate includes a chip area formed at an inward side of the semiconductor substrate when viewed in a direction perpendicular to a surface of the semiconductor substrate. The edge seal is disposed around the chip area on the surface to protect the chip area. The plurality of pad pieces are disposed on an edge region on the surface. The insulating film pattern covers edge portions of the plurality of pad pieces at a side of the edge seal, at least at one side of the chip area on the surface in a first direction and at least at one side of the chip area on the surface in a second direction.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shingo KOZAKI
  • Publication number: 20120064646
    Abstract: The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 15, 2012
    Inventors: Seigo NAKAMURA, Iwao Natori, Yasuhiro Motoyama
  • Publication number: 20120064644
    Abstract: A fluid ejection device includes one or more digital data storage arrays having plural EPROM cells. A method for affirming performance adequacy of EPROM cells in the one or more arrays includes the steps of identifying a reference cell in each array, measuring a selected performance criterion for the reference cells, obtaining a reference criterion value, and evaluating the actual performance of at least one cell in each array with respect to the reference criterion value.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Stan E. Leigh, Kevin Bruce, Joseph M. Torgerson, Trudy Benjamin
  • Publication number: 20120061853
    Abstract: A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Inventors: Michael Z. Su, Lei Fu, Gamal Refai-Ahmed Refai-Ahmed, Bryan Black
  • Publication number: 20120056288
    Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.
    Type: Application
    Filed: August 24, 2011
    Publication date: March 8, 2012
    Applicant: SONY CORPORATION
    Inventors: Ikuo Yoshihara, Taku Umebayashi, Hiroshi Takahashi, Hironobu Yoshida
  • Patent number: 8129203
    Abstract: A method of manufacturing integrated circuits includes measuring a reflectivity value of a wafer. An optimum energy level for laser marking the wafer is determined using the reflectivity value. A laser beam having the optimum energy level is then emitted to make laser marks on the wafer.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lan Fang Chang, Wei-Ming You
  • Publication number: 20120052601
    Abstract: Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.
    Type: Application
    Filed: July 11, 2011
    Publication date: March 1, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Dmytro Chumakov, Petra Hetzer, Matthias Schaller
  • Patent number: 8124428
    Abstract: A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 28, 2012
    Assignee: Imec
    Inventor: Gregory Van Barel