Abstract: A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer.

Abstract: A liquid crystal display, having an improved application of electric field to the molecules of liquid crystal, includes a substrate and a pixel array bonded to the surface of this substrate, and the pixel array includes at least a thin-film transistor and a pixel electrode connected with this thin-film transistor, and the pixel electrode is formed in a layer higher than the thin-film transistor in relation to the substrate.

Abstract: A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.

Abstract: An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract: Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: A method is described to create a thin semiconductor lamina adhered to a ceramic body. The method includes defining a cleave plane in a semiconductor donor body, applying a ceramic mixture to a first face of the semiconductor body, the ceramic mixture including ceramic powder and a binder, curing the ceramic mixture to form a ceramic body, and cleaving a lamina from the semiconductor donor body at the cleave plane, the lamina remaining adhered to the ceramic body. Forming the ceramic body this way allows outgassing of volatiles during the curing step. Devices can be formed in the lamina, including photovoltaic devices. The ceramic body and lamina can withstand high processing temperatures. In some embodiments, the ceramic body may be conductive.

Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.

Abstract: A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction.

Abstract: A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate.

Abstract: A method of manufacturing a liquid crystal display device of the present invention includes a color defect compensation process for compensating for a color defect if it is present in a color filter that includes color portions in a plurality of colors. The color defect compensation process includes specifying a compensation area in at least one of glass substrate among a pair of glass substrates, the compensation area that overlaps a shadow of a color defect occurrence area, which is a possible cause of the color defect, and the shadow projected on a glass substrate, doping metal ions that correspond to a color of the color portion that includes the color defect occurrence area in the compensation area of the glass substrate, which is specified, and forming a colored portion having the same color as the color portion that includes the color defect occurrence area in the compensation area.

Abstract: A package for an electronic chip including an optical component protects the chip and the component, while allowing for an optical connection of the component with another optical device. This is achieved, in various embodiments, by forming a well in a protective material deposited over the chip to expose the optical component, and by providing alignment features in the protective material to align and connect the optical component with another optical device.

Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

Abstract: The invention is based on a method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method is intended to avoid “front side to rear side” alignments. The proposed method for aligning the electronic CMOS structure uses the formation of alignment marks (7; 7a, 7b) in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer (1), which includes the structure (2) to be buried. The alignment marks (7) are formed on the edge of the semiconductor wafer. A cover wafer (5) is provided with first thinned portions (10a; 10b) of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks (7). A plan view of the alignment marks (7) is obtained after wafer bonding.

Abstract: A thin film transistor (“TFT”) array panel according to an exemplary embodiment of the present invention includes a substrate, a first storage electrode formed on the substrate, a first TFT formed on the substrate and separated from the first storage electrode, a first insulating layer formed on the first storage electrode and the first TFT and having a first opening disposed on the first storage electrode, a pixel electrode connected to the first TFT and overlapping the first storage electrode in the first opening, and a second insulating layer disposed between the first storage electrode and the pixel electrode in the first opening, wherein at least a portion of the boundary of the pixel electrode overlaps the first storage electrode and is disposed in the first opening. Accordingly, storage appropriate capacitance is ensured and a reduction of the aperture ratio may be decreased.

Abstract: Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.

Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

Abstract: Semiconductor wafer alignment markers and associated systems and methods are disclosed. A wafer in accordance with a particular embodiment includes a wafer substrate having an alignment marker that includes a first structure and a second structure, each having a pitch, with first features and second features positioned within the pitch. The first features are positioned to generate first phase portions of an interference pattern, with at least one of the first features having a width different than another of the first features in the pitch, and with the second features positioned to generate second phase portions of the interference pattern, with the second phase portions having a second phase opposite the first phase, and with at least one of the second features having a width different than that of another of the second features in the pitch. The pitch for the first structure is different than the pitch for the second structure.

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention.

Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate, along with a raised feature formed on the first or the second substrate. At least one of the metal layers may be deposited conformally over the raised feature. The raised feature penetrates the molten material of the first or the second metal layers during formation of the alloy, and produces a spectrum of stoichiometries for the formation of the desired alloy, as a function of the distance from the raised feature. At some distance from the raised feature, the proper ratio of the first metal to the second metal exists to form an alloy of the preferred stoichiometry.

Abstract: In a semiconductor device including a carbon-containing electrode and a method for fabricating the same, an electrode has a high work function due to a carbon-containing TiN layer contained therein. It is possible to provide a dielectric layer having a high permittivity and thus to reduce the leakage current by forming an electrode having a high work function. Also, sufficient capacitance of a capacitor can be secured by employing an electrode having a high work function and a dielectric layer having a high permittivity.

Abstract: A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe region configured to be formed among the plurality of chips so as to separate each chip, and an alignment key pattern configured to be arranged on the plurality of chips.

Abstract: A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern.

Abstract: A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

Abstract: A method for fabricating image sensor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a plurality of photodiodes; forming at least one dielectric layer and a passivation layer on surface of the substrate; using a patterned photomask to perform a first pattern transfer process for forming a plurality of trenches corresponding to each photodiode in the passivation layer; forming a plurality of color filters in the trenches; covering a planarizing layer on the color filters; and using the patterned photomask to perform a second pattern transfer process for forming a plurality of microlenses corresponding to each color filter on the planarizing layer.

Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

Abstract: In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.

Abstract: A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.

Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.

Abstract: An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a first stress film covering a first transistor arranged in a first region and a second transistor arranged in a second region on a semiconductor substrate; forming an etching stopper film, which possesses etching characteristics different from etching characteristics of the first stress film, on the first stress film; etching the etching stopper film to selectively leave the etching stopper film at a portion covering a sidewall portion of the first stress film in the first region; removing both the etching stopper film and the first stress film in the second region; and forming a second stress film, which possesses etching characteristics different from the etching characteristics of the etching stopper film, on the semiconductor substrate in such a manner as to cover the second transistor, the first stress film.

Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

Abstract: Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first side. A deflection structure is fabricated in the semiconductor chip. The deflection structure includes a sloped profile to deflect a crack propagating in the semiconductor chip toward the first side or the second side of the semiconductor chip.

Abstract: At a low temperature of 500° C. to 700° C., the concentration of atomic oxygen is controlled in a wafer stacked direction, and the thickness distribution of oxide films is kept uniform in the wafer stacked direction. A semiconductor device manufacturing method includes a process of oxidizing substrates by supplying oxygen-containing gas and hydrogen-containing gas through a mixing part from an end side of a substrate arrangement region where the substrates are arranged inside the process chamber so that the gases flow toward the other end side of the substrate arrangement region, and supplying hydrogen-containing gas from mid-flow locations corresponding to the substrate arrangement region.

Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode.

Abstract: The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.

Abstract: Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Abstract: Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

Abstract: An object is to prevent a reduction of definition (or resolution) (a peripheral blur) caused when reflected light enters a photoelectric conversion element arranged at a periphery of a photoelectric conversion element arranged at a predetermined address. A semiconductor device is manufactured through the steps of: forming a structure having a first light-transmitting substrate, a plurality of photoelectric conversion elements over the first light-transmitting substrate, a second light-transmitting substrate provided so as to face the plurality of photoelectric conversion elements, a sealant arranged so as to bond the first light-transmitting substrate and the second light-transmitting substrate and surround the plurality of photoelectric conversion elements; and thinning the first light-transmitting substrate by wet etching.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. One of the metal layer may have a diffusion barrier layer and a “keeper” layer formed thereover, wherein the keeper layers keeps the metal confined to a particular area. By using such a “keeper” layer, the substrate components may be heated to clean their surfaces, without activating or spending the bonding mechanism.

Abstract: A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the first substrate surface into the semiconductor substrate. The trench has a first trench section and a second trench section. The trench surface is exposed in an upper portion of the first and second trench sections and covered with a first insulating layer in a lower portion. A second insulating layer is formed at least on the exposed trench surface in the upper portion. A conductive layer is formed on the second insulating layer at least in the upper portion, wherein the second insulating layer electrically insulates the conductive layer from the semiconductor substrate. The conductive layer is removed in the first trench section without removing the conductive layer in the second trench section.