Making Of Isolation Regions Between Components (epo) Patents (Class 257/E21.54)

  • Patent number: 10522652
    Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Po-Wen Su, Chih-Wei Lin, Wei-Chih Lai, Tai-Yen Lin
  • Patent number: 10256137
    Abstract: An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
  • Patent number: 10134638
    Abstract: An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Yu-Lien Huang, You-Ru Lin
  • Patent number: 10002993
    Abstract: A light emitting device includes at least one semiconductor light emitting element, and a wavelength conversion layer which is formed on a surface of the semiconductor light emitting element and which includes a resin layer containing a wavelength conversion member for converting a wavelength of light emitted from the semiconductor light emitting element. The wavelength conversion layer covers an upper surface or the upper surface and a side surface of the semiconductor light emitting element. A content of an inorganic material including the wavelength conversion member, or a content of an inorganic material including the wavelength conversion member and an inorganic filler, in the resin layer is 30% by mass or more and 99% by mass or less.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 19, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Takeshi Ikegami, Hiroto Tamaki
  • Patent number: 9721845
    Abstract: Various embodiments disclose a method for fabricating one or more vertical fin field-effect-transistors. In one embodiment, a structure is formed. The structure comprises a substrate, a source/drain layer, and a plurality of fins formed on the first source/drain layer. The source/drain layer comprises a first semiconductor layer, a sacrificial layer, and a second semiconductor layer. A bottom spacer layer is formed in contact with the second semiconductor layer and the plurality of fins. A gate structure is then formed. A dielectric layer is deposited in contact with at least the gate structure, the bottom spacer layer, and the second semiconductor layer. At least a portion of the dielectric layer and a portion of the second semiconductor are removed. This removal forms a trench exposing a portion of the sacrificial layer. The sacrificial layer is then removed forming a cavity. A contact material is deposited within the trench and the cavity.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9716041
    Abstract: A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third regions, forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively, forming first and second dummy spacers on the first and second regions, respectively to form a first trench in the third region that exposes the third region, forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively, forming a dummy gate by filling the first and second trenches and removing the first and second dummy spacers.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Kang-Ill Seo
  • Patent number: 9698225
    Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9601504
    Abstract: A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 21, 2017
    Assignee: SK hynix Inc.
    Inventors: Hyun Ho Lee, Ji Hye Shin
  • Patent number: 9484376
    Abstract: The present disclosure provides a method for manufacturing a semiconductor isolation structure, including providing a substrate with a top surface; forming a patterned mask over the top surface; forming a trench through the patterned mask in the substrate by a directional etch comprising nitrogen-containing substance, wherein an aspect ratio of the trench is formed to be greater than about 18, and a ratio of a width of a narrowest portion and a width of a widest portion of the isolation region is formed to be greater than about 0.7; and filling the trench with insulating materials. The present disclosure also provides an image sensing device, including a radiation sensing region with a first isolation region separating adjacent radiation detecting units and a peripheral region, wherein an aspect ratio of the first isolation region is greater than about 18.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Yi Wang, Keng-Ying Liao, Po-Zen Chen, Yi-Hung Chen
  • Patent number: 9484298
    Abstract: A non-volatile memory device includes a first electrode layer extending in a first direction and a first channel body extending through the first electrode layer in a second direction. The first electrode layer has, on a side surface, a first projecting portion expanding in a third direction perpendicular to the first direction and the second direction, and having a rounding shape in a tip of the first projecting portion.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: November 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Noda, Tomohiro Yamada
  • Patent number: 9460956
    Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Ching-Feng Fu, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng
  • Patent number: 9293374
    Abstract: A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice structure and the substrate comprising a second material comprising a second lattice structure. Forming the one or more fin structures on the substrate includes forming one or more trenches in the substrate, and growing the first material in the one or more trenches. The first lattice structure is different from the second lattice structure. Forming one or more trenches comprises selecting a width of the trenches so as to at least partially reduce defects resulting from the lattice mismatch of the first and second materials. The one or more fin structures are self-aligned by the one or more trenches.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9029954
    Abstract: A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a semiconductor substrate, a first gate insulating film having a first high-dielectric-constant insulating film containing a first metal for adjustment, and a first electrode formed on the first gate insulating film. A protrusion amount of one end of the first high-dielectric-constant insulating film on the first device isolation part is smaller than a protrusion amount of an end of the first gate electrode above the first device isolation part.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Tomohiro Fujita
  • Patent number: 9024366
    Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Il Kim
  • Patent number: 9012300
    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wu-Sian Sie, Chun-Wei Hsu, Chia-Lung Chang, Chih-Hsun Lin, Chang-Hung Kung, Yu-Ting Li, Wei-Che Tsao, Yen-Ming Chen, Chun-Hsiung Wang, Chia-Lin Hsu
  • Patent number: 8999736
    Abstract: A method of making an optoelectronic system in accordance with the present disclosure is disclosed. The method includes providing a temporary substrate; providing un-packaged optoelectronic elements having sidewalls, top surfaces, and bottom surfaces, at least one of the unpackaged optoelectronic elements having an electrode provided on a side of the bottom surfaces; attaching the bottom surfaces to the temporary substrate such that a trench is formed between two of the un-packaged optoelectronic elements; providing an adhesive material to fully fill the trench and cover the un-packaged optoelectronic elements such that the sidewalls and top surfaces of the un-packaged optoelectronic elements are fully enclosed by the adhesive material; providing a transparent substrate on the adhesive material; and removing the temporary substrate without removing all the adhesive material covering the optoelectronic elements.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: April 7, 2015
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Cheng-Nan Han, Steve Meng-Yuan Hong, Hsin-Mao Liu, Tsung-Xian Lee
  • Patent number: 8994082
    Abstract: Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chi Hung, Jhy-Jyi Sze, Shou-Gwo Wuu
  • Patent number: 8987791
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Patent number: 8921188
    Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ram Asra
  • Patent number: 8921183
    Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Jen-Jui Huang, Hung-Ming Tsai
  • Patent number: 8907444
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu
  • Patent number: 8871560
    Abstract: Embodiments relate to a method for annealing a solar cell structure including forming an absorber layer on a molybdenum (Mo) layer of a solar cell base structure. The solar cell base structure includes a substrate and the Mo layer is located on the substrate. The absorber layer includes a semiconductor chalcogenide material. Annealing the solar cell base structure is performed by exposing an outer layer of the solar cell base structure to a plasma.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shafaat Ahmed, Sukjay Chey, Hariklia Deligianni, Lubomyr T. Romankiw
  • Patent number: 8865560
    Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Shien Mor, Hsiao-Chu Chen, Mu-Chi Chiang
  • Patent number: 8846492
    Abstract: An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang
  • Patent number: 8828830
    Abstract: A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ookura
  • Patent number: 8815698
    Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8803213
    Abstract: Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul Grisham
  • Patent number: 8785290
    Abstract: A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroaki Naruse
  • Patent number: 8772126
    Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 8748275
    Abstract: In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Stephan Kronholz, Maciej Wiatr
  • Patent number: 8742590
    Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 3, 2014
    Assignee: IMEC
    Inventor: Eric Beyne
  • Patent number: 8736036
    Abstract: A process is described for wavelength conversion of LED light using phosphors. LED dies are tested for correlated color temperature (CCT), and binned according to their color emission. The LEDs in a single bin are mounted on a single submount to form an array of LEDs. Various thin sheets of a flexible encapsulant (e.g., silicone) infused with one or more phosphors are preformed, where each sheet has different color conversion properties. An appropriate sheet is placed over an array of LED mounted on a submount, and the LEDs are energized. The resulting light is measured for CCT. If the CCT is acceptable, the phosphor sheet is permanently laminated onto the LEDs and submount. The lamination encapsulates each LED to protect the LEDs from contaminants and damage. The LEDs in the array of LEDs on the submount are separated. By selecting a different phosphor sheet for each bin of LEDs, the resulting CCT is very uniform across all bins.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: May 27, 2014
    Assignee: Philips Lumileds Lighting Company LLC
    Inventor: Haryanto Chandra
  • Publication number: 20140127877
    Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. Green, Marwan H. Khater, Yurii A. Vlasov
  • Patent number: 8716074
    Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Witold Maszara, Hemant Adhikari
  • Patent number: 8703577
    Abstract: A method for fabricating a deep trench isolation structure, wherein the method comprising steps as follows: A first hard mask layer, a second hard mask layer and a third hard mask layer are firstly formed in sequence on a substrate. The third hard mask layer is then patterned using the second hard mask layer as an etching stop layer. Subsequently, a trench etching process is performed using the patterned third hard mask layer as a mask to form a deep trench in the substrate.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 22, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Meng-Kai Zhu
  • Publication number: 20140091381
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 3, 2014
    Applicant: SANDISK 3D, LLC
    Inventor: Donovan Lee
  • Patent number: 8685830
    Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Zhou, Jia Pan, Hao Li, Yongcheng Wang
  • Patent number: 8679938
    Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang
  • Patent number: 8680644
    Abstract: A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Coroporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Tenko Yamashita, Ying Zhang
  • Patent number: 8673735
    Abstract: A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Tenko Yamashita, Ying Zhang
  • Publication number: 20140070358
    Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Puneet Khanna, Srikanth Samavedam, Vara G. Vakada, Michael P. Ganz, Sri Charan Vemula, Laegu Kang, Bharat V. Krishnan
  • Publication number: 20140070365
    Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Inventors: Lakshminarayan Viswanathan, Jeffrey K. Jones, Scott D. Marshall
  • Patent number: 8664062
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • Publication number: 20140054699
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicants: STMicroelectronics, Inc., COMMISSARIATE A ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: QING LIU, PRASANNA KHARE, NICOLAS LOUBET, SHOM PONOTH, MAUD VINET, BRUCE DORIS
  • Publication number: 20140051225
    Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8652884
    Abstract: The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: February 18, 2014
    Assignee: The Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang
  • Publication number: 20140045318
    Abstract: Processes for forming a tapered field plate dielectric in a semiconductor substrate are provided. The process may be used to form a variety of types of devices, such as Schottky diodes, HVFETs, JFET, IGBT, bipolar transistors, and the like. The process may include etching a trench in a semiconductor wafer, depositing an insulating layer on the semiconductor wafer to form a gap within the trench, depositing a masking layer on the insulating layer, and alternatingly etching the masking layer and the insulating layer to form a tapered field plate dielectric region.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: Power Integrations, Inc.
    Inventors: Vijay PARTHASARATHY, Wayne B. GRABOWSKI
  • Publication number: 20140030868
    Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Wayne B. Grabowski
  • Publication number: 20140022844
    Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott