Abstract: In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.

Abstract: In annealing of a non-single crystal silicon film by a linear laser beam, it is performed so as irradiation tracks caused by the linear laser beam do not remain in the silicon film. Laser light is partitioned by an integrally formed cylindrical array lens, and is composed into a single uniform laser beam on an irradiation surface by a cylindrical lens and a doublet cylindrical lens. The integrally formed cylindrical array lens is used, and therefore cylindrical lenses structuring this array lens can be made very fine. It thus becomes possible to partition the laser light into a large number of partitions, and the uniformity of the laser beam on the irradiation surface is increased. Very few laser irradiation tracks remain on the silicon film annealed by the very uniform laser beam.

Abstract: Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract: Some embodiments comprise a plurality of fins, wherein at least a first fin of the plurality of fins comprises a different fin width compared to a fin width of another fin of the plurality of fins. At least a second fin of the plurality of fins comprises a different crystal surface orientation compared to another fin of the plurality of fins.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.

Abstract: A mask for sequential lateral solidification (SLS) processes including at least one first window, one second window, one third window, and one fourth window is provided. Each window has a length extending longitude on the mask. The second window is aligned to the first window. The width of the first window is greater than that of the second window. The fourth window is aligned to the third window. The width of the third window is greater than that of the fourth window.

Abstract: It is an object to provide a method for manufacturing an SOI substrate in which reduction in yield can be suppressed while impurity diffusion into a semiconductor film is suppressed. A semiconductor substrate provided with an oxide film is formed by thermally oxidizing the surface of the semiconductor substrate. Plasma is generated under an atmosphere of a gas containing nitrogen atoms and plasma nitridation is performed on part of the oxide film, so that a semiconductor substrate in which an insulating film containing nitrogen atoms is formed over the oxide film is obtained. After bonding the insulating film containing nitrogen atoms and a glass substrate to each other, the semiconductor substrate is split, whereby an SOI substrate in which the insulating film containing nitrogen atoms, the oxide film, a thin semiconductor film are stacked in this order is formed.

Abstract: An object is to provide a method for manufacturing an SOI substrate including a semiconductor film with high planarity and high crystallinity. After a single crystal semiconductor film is formed over an insulating film by a separation step, a natural oxide film existing on a surface of the semiconductor film is removed and the semiconductor film is irradiated with first laser light and second laser light under an inert gas atmosphere or a reduced-pressure atmosphere. The number of shots of the first laser light that is emitted to an arbitrary point in the semiconductor film is greater than or equal to 7, preferably greater than or equal to 10 and less than or equal to 100. The number of shots of the second laser light that is emitted to an arbitrary point in the semiconductor film is greater than 0 and less than or equal to 2.

Abstract: To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.

Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.

Abstract: Methods and apparatus for producing a semiconductor on glass (SOG) structure include: bringing a first surface of a glass substrate into direct or indirect contact with a semiconductor wafer; heating at least one of the glass substrate and the semiconductor wafer such that a second surface of the glass substrate, opposite to the first surface thereof, is at a lower temperature than the first surface; applying a voltage potential across the glass substrate and the semiconductor wafer; and maintaining the contact, heating and voltage to induce an anodic bond between the semiconductor wafer and the glass substrate via electrolysis.

Abstract: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

Abstract: Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof.

Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Abstract: A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.

Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

Abstract: Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.

Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel TFT and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

Abstract: The present disclosure relates to methods and apparatuses for releasing a thin semiconductor substrate from a reusable template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: A method for producing an epitaxial layer. First, a structure is fabricated by: formation of an intermediate layer on a donor substrate; and formation of the epitaxial layer on the intermediate layer by epitaxy; with the melting temperature of the intermediate layer being lower than the melting temperature of the epitaxial layer; and then a detachment step for transferring the epitaxial layer from the donor substrate. The detachment step includes applying at least one thermal treatment performed at a temperature of between the melting temperature of the intermediate layer and the melting temperature of the epitaxial layer.

Abstract: A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.

Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.

Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.

Abstract: The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single electron transistor operating at room temperature, in which a quantum dot or a silicide quantum dot using a nanostructure is formed and a gate is positioned on the quantum dot so as to minimize influence on a tunneling barrier and achieve improved effectiveness in electric potential control for the quantum dot and operating efficiency of the transistor, and a manufacturing method for same.

Abstract: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.

Abstract: The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.

Abstract: The present invention provides a beam homogenizer for homogenizing energy distribution by making the distance between lenses small to shorten the optical path length with the use of an array lens of an optical path shortened type, and a laser irradiation apparatus using the beam homogenizer. The beam homogenizer is equipped with a front side array lens of an optical path shortened type whose second principal point is positioned ahead on a beam incidence side, a back side array lens of an optical path shortened type whose first principal point is positioned behind on a beam emission side, and a condensing lens, wherein the distance between the second principal point of the front side array lens and the first principal point of the back side array lens is equal to the focal length of the back side array lens.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

Abstract: A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A method of fabricating a thin film transistor, in which source and drain electrodes are formed through a solution process, even all stages which include formation of electrodes on a substrate, formation of an insulator layer, and formation of an organic semiconductor layer are conducted through the solution process. In the method, the fabrication is simplified and a fabrication cost is reduced. It is possible to apply the organic thin film transistor to integrated circuits requiring high speed switching because of high charge mobility.

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract: A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. Compared to conventional structures of thin film transistors, the structure of the present invention uses a patterned first metal layer as a data line, and a patterned second metal layer as a gate line. In a thin film transistor, a gate is also located in the patterned first metal layer, and is electrically connected to the gate line located in the patterned second metal layer through a contact hole. A source and a drain of the thin film transistor are electrically connected to the data line through a contact hole. The structure of the present invention increases a storage capacitance and an aperture ratio.

Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: An embodiment of a laser crystallization method includes providing a substrate on which an amorphous silicon thin film is deposited, positioning a laser mask over the substrate, the laser mask including a mask pattern that contains transmitting regions and a blocking region, irradiating a first laser beam onto a surface of the substrate through the pattern of the laser mask to first crystallize a predetermined region of the silicon thin film, moving the laser mask or a stage on which the substrate is loaded in an X-axis direction to perform second crystallization using the laser mask, repeatedly performing the crystallization to an end of the substrate in the X-axis direction, moving the laser mask or the stage in a Y-axis direction, and repeatedly performing the crystallization in the Y-axis direction to complete crystallization.

Abstract: Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X-and Y-axial directions.

Abstract: A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.

Abstract: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

Abstract: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Abstract: An island-shaped single crystal semiconductor layer whose top surface has a plane within ±10° from a {211} plane is formed on an insulating surface; a non-single-crystal semiconductor layer is formed in contact with the top surface and a side surface of the single crystal semiconductor layer and on the insulating surface; the non-single-crystal semiconductor layer is irradiated with laser light to melt the non-single-crystal semiconductor layer, and to crystallize the non-single-crystal semiconductor layer formed on the insulating surface with use of the single crystal semiconductor layer as a seed crystal, so that a crystalline semiconductor layer is formed. A semiconductor device having an n-channel transistor and a p-channel transistor formed with use of the crystalline semiconductor layer is provided.

Abstract: A single crystal semiconductor separated from a single crystal semiconductor substrate is formed partly over a supporting substrate with a buffer layer provided therebetween. The single crystal semiconductor is separated from the single crystal semiconductor substrate by irradiation with accelerated ions, formation of a fragile layer by the ion irradiation, and heat treatment. A non-single crystal semiconductor layer is formed over the single crystal semiconductor and irradiated with a laser beam to be crystallized, whereby an SOI substrate is manufactured.

Abstract: A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

Abstract: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized using silicides having different densities such that the active layer of the driving transistor has a larger grain size than the active layer of the switching layer.