Using Bonding Technique (epo) Patents (Class 257/E21.567)
  • Publication number: 20130084687
    Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 4, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien CUZZOCREA, Laurent-Luc CHAPELON
  • Publication number: 20130069195
    Abstract: According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 21, 2013
    Inventor: Kyoichi Suguro
  • Publication number: 20130071996
    Abstract: When joining a processing target substrate and a supporting substrate together by suction-holding the processing substrate and the supporting substrate respectively on a first holding unit and a second holding unit arranged to face each other and pressing the second holding unit toward the first holding unit while heating the substrates by heating mechanisms of the holding units, the present invention preheats at least the processing target substrate before suction-holding the processing target substrate on the first holding unit to suppress generation of particles when joining the processing target substrate and the supporting substrate together so as to properly perform the joining of the processing target substrate and the supporting substrate.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 21, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masatoshi DEGUCHI, Masatoshi SHIRAISHI, Shinji OKADA
  • Patent number: 8399336
    Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
  • Publication number: 20130048480
    Abstract: A structure for a signal line has the signal line having a base, a lower insulating layer formed at an upper surface of the base, a semiconductor layer disposed along a pathway at an upper surface of the lower insulating layer, at least a part of the semiconductor layer configured to transmit a signal, an upper insulating layer formed at an upper surface of the semiconductor layer, at least a part of the upper insulating layer being mounted along the semiconductor layer; and a strip conductor formed at an upper surface of the upper insulating layer, at least a part of the strip conductor being mounted along the upper insulating layer.
    Type: Application
    Filed: December 9, 2010
    Publication date: February 28, 2013
    Applicant: OMRON CORPORATION
    Inventors: Junya Yamamoto, Koji Narise
  • Patent number: 8383452
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
  • Patent number: 8367440
    Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
  • Publication number: 20130029475
    Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 31, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Takeo TSUKAMOTO
  • Publication number: 20130023082
    Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.
    Type: Application
    Filed: September 20, 2012
    Publication date: January 24, 2013
    Applicant: Analog Devices, Inc.
    Inventor: Analog Devices, Inc.
  • Publication number: 20130020704
    Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 24, 2013
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Mariam Sadaka
  • Patent number: 8357586
    Abstract: Provided is a method for manufacturing an SOI wafer, which is capable of: efficiently removing an ion-implanted defect layer existing in an ion implanted layer in the vicinity of a peeled surface peeled by an ion implantation peeling method; ensuring the in-plane uniformity of a substrate; and also achieving cost reduction and higher throughput. The method for manufacturing an SOI wafer includes at least the steps of: bonding a silicon wafer with or without an oxide film onto a handle wafer to prepare a bonded substrate, wherein the silicon wafer has an ion implanted layer formed by implanting hydrogen ions and/or rare gas ions into the silicon wafer; peeling the silicon wafer along the ion implanted layer, thereby transferring the silicon wafer onto the handle wafer to produce a post-peeling SOI wafer; immersing the post-peeling SOI wafer in an aqueous ammonia-hydrogen peroxide solution; and performing a heat treatment at a temperature of 900° C.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 22, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuji Tobisaka, Hiroshi Tamura
  • Patent number: 8349703
    Abstract: The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 ? in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: January 8, 2013
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Willy Michel, Walter Schwarzenbach, Daniel Delprat, Nadia Ben Mohamed
  • Publication number: 20120326268
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20120329241
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.
    Type: Application
    Filed: March 16, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
  • Patent number: 8338268
    Abstract: A transfer process for silicon nanomembranes (SiNM) may involve treating a recipient substrate with a polymer structural support. After treating the recipient substrate, a substrate containing the intended transferable devices may be brought in direct contact with the aforementioned polymer layer. The two substrates may then go through a Deep Reactive Ion Etch (DRIE) to remove at least a portion of the substrate containing the devices. Oxide may be selectively removed with a buffered oxide wet etch, leaving the transferred SiNM on the recipient substrate with the Underlying polymer layer.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Lumilant, Inc.
    Inventors: Mathew Joseph Zablocki, Ahmed Sharkawy, Dennis W. Prather
  • Publication number: 20120322228
    Abstract: A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshihiro KOMATSU, Tomoaki MORIWAKA, Kojiro TAKAHASHI
  • Publication number: 20120306032
    Abstract: Disclosed is a method for bonding semiconductor substrates, wherein an eutectic alloy does run off the bonding surfaces during the eutectic bonding. Also disclosed is an MEMS device which is obtained by bonding semiconductor substrates by this method. Specifically, a substrate (11) and a substrate (21) are eutectically bonded with each other by pressing and heating the substrate (11) and the substrate (21), while interposing an aluminum-containing layer (31) and a germanium layer (32) between a bonding part (30a) of the substrate (11) and a bonding part (30b) of the substrate (21) in such a manner that the aluminum-containing layer (31) and the germanium layer (32) overlap each other, with an outer edge (32a) of the germanium layer (32) being inwardly set back from the an outer edge (31a) of the aluminum-containing layer (31).
    Type: Application
    Filed: December 11, 2009
    Publication date: December 6, 2012
    Applicants: PIONEER MICRO TECHNOLOGY CORPORATION, PIONEER CORPORATION
    Inventors: Naoki Noda, Toshio Yokouchi, Masahiro Ishimori
  • Patent number: 8324075
    Abstract: The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Cecile Aulnette, Khalid Radouane
  • Patent number: 8324013
    Abstract: An organic layer of an organic light emitting diode (OLED) display device is formed by transferring a transfer layer of a donor film to aligned pixel openings in a pixel defining region of the OLED display device such that the organic layer is formed in the pixel openings. Each aligned pixel opening has a pair of long sides and a pair of short sides, and the transferring of the transfer layer is performed by applying tensile force to the donor film in a direction perpendicular to the short sides of the pixel openings.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 4, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Won Sun, Tae-Min Kang, Sang-Bong Lee
  • Publication number: 20120299147
    Abstract: After depressed portions (4) have been formed in advance in that surface of a Si substrate (1) on which Si single films (8) are to be formed, that surface of the Si substrate (1) on which the Si single films are to be formed and an intermediate substrate (5) are bonded together, and elements are separated from each other by grinding the Si substrate (1) from the bottom wall side of the depressed portions (4).
    Type: Application
    Filed: January 17, 2011
    Publication date: November 29, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Mitani
  • Publication number: 20120292777
    Abstract: In a stacked die device having an active circuit die bonded on top of a power delivery die using, circuit components formed on the active circuit die are connected to receive power from a coarse network of low resistance, high capacitance power and ground conductors in the power delivery die through conductive via structures or through silicon vias (TSVs) formed in the active circuit die so that primary power is provided from the backside of the active circuit die, leaving more resources and space in the metal interconnect structure for input/output signal routing.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Inventor: Jonathan P. Lotz
  • Publication number: 20120292748
    Abstract: The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure.
    Type: Application
    Filed: January 4, 2011
    Publication date: November 22, 2012
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Radu Ionut
  • Publication number: 20120289025
    Abstract: A method for manufacturing a bonded wafer including bonding together a bond wafer and a base wafer each having a chamfered portion at an outer circumference and thinning the bond wafer, wherein the thinning of the bond wafer includes: a first step of performing surface grinding on the bond wafer such that a thickness of the bond wafer reaches a first predetermined thickness; a second step of removing an outer circumference portion of the ground bond wafer; and a third step of performing surface grinding on the bond wafer such that the thickness of the bond wafer reaches a second predetermined thickness.
    Type: Application
    Filed: December 27, 2010
    Publication date: November 15, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Tadahiro Kato
  • Patent number: 8309429
    Abstract: A plurality of single crystal semiconductor substrates are arranged and then the plurality of single crystal semiconductor substrates which have been arranged are overlapped with a base substrate, so that the base substrate and the plurality of single crystal semiconductor substrates are bonded to each other. Then, each of the plurality of single crystal semiconductor substrates is separated to form a plurality of single crystal semiconductor layers over the base substrate. Next, in order to reduce crystal defects in the plurality of single crystal semiconductor layers, the plurality of single crystal semiconductor layers are irradiated with a laser beam. The plurality of single crystal semiconductor layers are thinned by being etched before or after irradiation with a laser beam.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: November 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8309970
    Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: November 13, 2012
    Assignee: Samsung Led Co., Ltd.
    Inventors: Myong Soo Cho, Ki Yeol Park, Sang Yeob Song, Si Hyuk Lee, Pun Jae Choi
  • Publication number: 20120276715
    Abstract: A connected substrate having a supporting portion and first and second silicon carbide substrates is prepared. The first silicon carbide substrate has a first backside surface connected to the supporting portion, a first front-side surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. The second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A filling portion for filling the gap is formed. Then, the first and second front-side surfaces are polished. Then, the filling portion is removed. Then, a closing portion for closing the gap is formed.
    Type: Application
    Filed: June 17, 2011
    Publication date: November 1, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES LTD.
    Inventors: Tsutomu Hori, Shin Harada, Makoto Sasaki, Hiroki Inoue, Kyoko Okita, Yasuo Namikawa, Satomi Itoh
  • Patent number: 8298916
    Abstract: The invention relates to a process for fabricating a multilayer structure comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800-mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: October 30, 2012
    Assignee: Soitec
    Inventors: Alexandre Vaufredaz, Sebastien Molinari
  • Publication number: 20120256290
    Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 11, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Crocifisso Marco Antonio Renna, Antonino Scuderi, Carlo Magro, Nunzio Spina, Egidio Ragonese, Barbaro Marano, Giuseppe Palmisano
  • Publication number: 20120256311
    Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 11, 2012
    Inventors: Kenichi TAKEDA, Mayu AOKI, Kazuyuki HOZAWA
  • Publication number: 20120248622
    Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Mariam Sadaka
  • Publication number: 20120248544
    Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 4, 2012
    Applicant: Sony Corporation
    Inventor: Takashi Yokoyama
  • Publication number: 20120252189
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru
  • Publication number: 20120248401
    Abstract: A three-dimensional graphene structure, and methods of manufacturing and transferring the same including forming at least one layer of graphene having a periodically repeated three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three-dimensional shape on a surface of a substrate, and forming the three-dimensional graphene structure having the three-dimensional shape of the pattern by growing graphene on the substrate on which the pattern is formed. The three-dimensional graphene structure is transferred by injecting a gas between the three-dimensional graphene structure and the substrate, separating the three-dimensional graphene structure from the substrate by bonding the three-dimensional graphene structure to an adhesive support, combining the three-dimensional graphene structure with an insulating substrate, and removing the adhesive support.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 4, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Ji-hoon Park, Joung-real Ahn
  • Publication number: 20120244678
    Abstract: A semiconductor device wafer bonding method bonds a first semiconductor device wafer having a plurality of semiconductor devices with a plurality of projecting electrodes to a second semiconductor device wafer having a plurality of electrodes respectively corresponding to the projecting electrodes of the first semiconductor device wafer. An insulator is applied and fills the spacing between adjacent projecting electrodes. The first semiconductor device wafer is planarized to expose the end surfaces of the projecting electrodes, and the first semiconductor device wafer is bonded to the second semiconductor device wafer with an anisotropic conductor interposed between the projecting electrodes of the first semiconductor device wafer and the electrodes of the second semiconductor device wafer, to thereby respectively connect the electrodes through the anisotropic conductor.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 27, 2012
    Applicant: DISCO CORPORATION
    Inventor: Takashi Mori
  • Publication number: 20120244677
    Abstract: The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Lin, Ping-Yin Liu, Lan-Lin Chao, Jung-Huei Peng, Chia-Shiung Tsai
  • Publication number: 20120228613
    Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Yuki SEKI, Issei Satoh, Koji Uematsu, Yoshiyuki Yamamoto
  • Publication number: 20120223431
    Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.
    Type: Application
    Filed: April 11, 2011
    Publication date: September 6, 2012
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Chao Zhao, Dapeng Chen, Wen Ou
  • Publication number: 20120220064
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Calvin Wade Sheen
  • Publication number: 20120217610
    Abstract: A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Inventors: Peter J. Hopper, Peter Johnson, Luu Nguyen, Peter Smeys
  • Publication number: 20120220101
    Abstract: The invention provides advances in the arts with useful and novel methods for assembling multi-layer semiconductor structures having one or more internal conductive layers. The disclosed structures provide advantages in terms of resistance to Single Event Effects (SEE) particularly useful in electronics designed for radiation hardness. Disclosed methods include steps for providing two semiconductor layers, each having a conductive surface, and bonding them together with their conductive surfaces adjoining in order to form an internal conductive layer within a completed multi-layer structure. The conductive surfaces may include metals selected for their superior conductivity, refractory metals, selected primarily for their heat-resistance, or conductive dopants. In alternative embodiments, vertical interconnects are also included.
    Type: Application
    Filed: August 27, 2011
    Publication date: August 30, 2012
    Applicant: TRIUNE IP LLC
    Inventors: Ross Teggatz, Wayne Chen, John Krick
  • Publication number: 20120217638
    Abstract: By forming a metal layer 14 on at least one of a connecting electrode 12 of a first substrate 10 and a connecting electrode 17 of a second substrate 15, placing the first substrate 10 and the second substrate 15 together in order that the connecting electrode 12 and the connecting electrode 17 face opposite to each other via the metal layer 14, increasing temperature up to anodic bonding temperature, and applying DC voltage between the first substrate 10 and the second substrate 15 while maintaining that temperature, the first substrate 10 and the second substrate 15 are anodically bonded, and at the same time by melting the metal layer 14, the connecting electrode 12 and the connecting electrode 17 are electrically connected. The method achieves anodic bonding of substrates with high yield and at the same time establishes wiring connection, effective for packaging.
    Type: Application
    Filed: September 1, 2010
    Publication date: August 30, 2012
    Applicant: TOHOKU UNIVERSITY
    Inventors: Shuji Tanaka, Masayoshi Esashi, Sakae Matsuzaki, Mamoru Mori
  • Publication number: 20120211770
    Abstract: There are provided a semiconductor device of low cost and high quality, a combined substrate used for manufacturing the semiconductor device, and methods for manufacturing them. The method for manufacturing the semiconductor device includes the steps of: preparing a single-crystal semiconductor member; preparing a supporting base; connecting the supporting base and the single-crystal semiconductor member to each other through a connecting layer containing carbon; forming an epitaxial layer on a surface of the single-crystal semiconductor member; forming a semiconductor element using the epitaxial layer; separating the single-crystal semiconductor member from the supporting base by oxidizing and accordingly decomposing the connecting layer after the step of forming the semiconductor element; and dividing the single-crystal semiconductor member separated from the supporting base.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 23, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Hideto Tamaso
  • Publication number: 20120211849
    Abstract: A method for manufacturing a semiconductor device including: forming a wiring layer on a surface side of a first semiconductor wafer; forming a buried film so as to fill in a level difference on the wiring layer, the level difference being formed at a boundary between a peripheral region of the first semiconductor wafer and an inside region being on an inside of the peripheral region, and the level difference being formed as a result of a surface over the wiring layer in the peripheral region being formed lower than a surface over the wiring layer in the inside region, and making the surfaces over the wiring layer in the peripheral region and the inside region substantially flush with each other; and opposing and laminating the surfaces over the wiring layer formed in the first semiconductor wafer to a desired surface of a second semiconductor wafer.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 23, 2012
    Applicant: SONY CORPORATION
    Inventor: Hiroyasu Matsugai
  • Publication number: 20120214291
    Abstract: A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 23, 2012
    Applicant: SOITEC
    Inventors: Fabrice Letertre, Carlos Mazure, Michael R. Krames, Melvin B. McLaurin, Nathan F. Gardner
  • Patent number: 8247307
    Abstract: A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 8241932
    Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 14, 2012
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chih-Kuang Yu, Chyi Shyuan Chern, Hsing-Kuo Hsia, Hung-Yi Kuo
  • Publication number: 20120202337
    Abstract: Provided is a sheet for processing a wafer. The sheet can exhibit excellent heat resistance and dimensional stability, prevent breakage of a wafer in response to residual stress due to excellent stress relaxation properties, inhibit damage to or dispersion of the wafer due to application of a non-uniform pressure, and also exhibit excellent cuttability. The sheet can effectively prevent a blocking phenomenon from occurring during wafer processing. For these reasons, the sheet can be useful for processing a wafer in various wafer preparation processes such as dicing, back-grinding and picking-up.
    Type: Application
    Filed: December 14, 2011
    Publication date: August 9, 2012
    Applicant: LG CHEM, LTD.
    Inventors: SE RA KIM, HYO SOOK JOO, SUK KY CHANG, JUNG SUP SHIM
  • Patent number: 8237252
    Abstract: A semiconductor device is made by forming a first thermally conductive layer over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Publication number: 20120193773
    Abstract: A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Inventor: Nilesh Kapadia
  • Publication number: 20120171809
    Abstract: A method for producing a lamina from a donor body includes implanting the donor body with an ion dosage and heating the donor body to an implant temperature during implanting. The donor body is separably contacted with a susceptor assembly, where the donor body and the susceptor assembly are in direct contact. A lamina is exfoliated from the donor body by applying a thermal profile to the donor body. Implantation and exfoliation conditions may be adjusted in order to maximize the defect-free area of the lamina.
    Type: Application
    Filed: December 20, 2011
    Publication date: July 5, 2012
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Adam Kell, Robert Clark-Phelps, Joseph D. Gillespie, Gopal Prabhu, Takao Sakase, Theodore H. Smick, Steve Zuniga, Steve Bababyan