With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
  • Patent number: 8778775
    Abstract: A method for preparing a thin layer of GaN from a starting substrate in which at least one thick surface area extending along a free face of the starting substrate includes GaN, where the method includes bombarding the free face of the substrate with helium and hydrogen atoms, the helium being implanted first into the thickness of the thick surface area and the hydrogen being implanted thereafter, and where the helium and hydrogen doses each vary between 1.1017 atoms/cm2 and 4.1017 atoms/cm2. The starting substrate is subjected to a rupture process in order to induce the separation, relative to a residue of the starting substrate, of the entire portion of the thick area located between the free face and the helium and hydrogen implantation depth. The helium is advantageously implanted in a dose at least equal to that of hydrogen, and can also be implanted alone.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: July 15, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Aurélie Tauzin, Jérôme Dechamp, Frédéric Mazen, Florence Madeira
  • Patent number: 8778771
    Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuo Kokumai
  • Patent number: 8772129
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8772130
    Abstract: In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal to 200° C. In addition, the semiconductor substrate is subjected to plasma treatment while the semiconductor substrate is kept at a temperature of higher than or equal to 100° C. and lower than or equal to 400° C. after the hydrogen ion addition treatment, whereby Si—H bonds which have low contribution to separation of the semiconductor thin film layer can be reduced while Si—H bonds which have high contribution to separation of the semiconductor thin film layer, which are generated by the hydrogen ion addition treatment, are kept.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroshi Ohki
  • Patent number: 8765535
    Abstract: In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 8765576
    Abstract: A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate; heat-treating the laminated substrate and diffusing outwardly the oxide film.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: July 1, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Atsuo Ito, Yoshihiro Kubota, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8765508
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8759195
    Abstract: An optical device layer (ODL) in an optical device wafer is transferred to a transfer substrate. The ODL is formed on the front side of an epitaxy substrate through a buffer layer. The ODL is partitioned by a plurality of crossing streets to define regions where a plurality of optical devices are formed. The transfer substrate is bonded to the front side of the ODL, and the epitaxy substrate is cut along crossing streets into a plurality of blocks. A laser beam is applied to the epitaxy substrate from the back side of the epitaxy substrate to the unit of the optical device wafer and the transfer substrate in the condition where the focal point of the laser beam is set in the buffer layer, thereby decomposing the buffer layer. The epitaxy substrate divided into the plurality of blocks is peeled off from the ODL.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 24, 2014
    Assignee: Disco Corporation
    Inventors: Hiroshi Morikazu, Yoko Nishino
  • Patent number: 8759196
    Abstract: A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach the detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Soitec
    Inventor: Michel Bruel
  • Patent number: 8748294
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8748243
    Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8741740
    Abstract: An SOI substrate is manufactured by forming an embrittled layer in a bond substrate by increasing the dose of hydrogen ions in the formation of the embrittled layer to a value more than the dose of hydrogen ions of the lower limit for separation of the bond substrate, separating the bond substrate attached to the base substrate, forming an SOI substrate in which a single crystal semiconductor film is formed over the base substrate, and irradiating a surface of the single crystal semiconductor film with laser light.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hajime Tokunaga
  • Patent number: 8741741
    Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength ? comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: June 3, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Susumu Kuwabara
  • Patent number: 8735264
    Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hiroyuki Yasuda, Masahiro Furuya, Michihiro Sugo, Shohei Tagami, Hideyoshi Yanagisawa
  • Patent number: 8735263
    Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kazuya Hanaoka
  • Patent number: 8728912
    Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Satoshi Oka
  • Patent number: 8716106
    Abstract: A method for producing a bonded substrate having a Si1-xGex (0<x?1) film in which a larger than ever biaxial strain has been introduced. Specifically, the method involves at least the steps of: providing a donor wafer and a handle wafer having a thermal expansion coefficient lower than the donor wafer, implanting ions of any one or both of hydrogen and a noble gas into the donor wafer to form an ion-implanted layer, performing a plasma activation treatment on at least one of bonding surfaces of the donor wafer and the handle wafer, bonding the donor wafer to the handle wafer, splitting the donor wafer through application of a mechanical impact to the ion-implanted layer, performing a surface treatment on a split surface of the donor wafer, and epitaxially growing a Si1-xGex (0<x?1) film on the split surface to thus form a strained Si1-xGex (0<x?1) film on the bonded wafers.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: May 6, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8709914
    Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 8703521
    Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma Sosa Cortes, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi
  • Patent number: 8703580
    Abstract: In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 22, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Yoshihiro Kubota, Kiyoshi Mitani
  • Patent number: 8697544
    Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto
  • Publication number: 20140084454
    Abstract: A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: APPLE INC.
    Inventors: Shawn X. ARNOLD, Matthew E. LAST
  • Patent number: 8664085
    Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoko Maeda, Fumitaka Sato, Akihiro Hachigo, Seiji Nakahata
  • Patent number: 8652925
    Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
  • Patent number: 8648423
    Abstract: Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hee Han, Soo-Ho Shin
  • Publication number: 20140030836
    Abstract: A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: Twin Creeks Technologies, Inc.
    Inventors: Venkatesan Murali, Steve Babayan, Christopher J. Petti
  • Patent number: 8633090
    Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.
    Type: Grant
    Filed: July 10, 2010
    Date of Patent: January 21, 2014
    Assignees: Shanghai Simgui Technology Co., Ltd., Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xiang Wang, Xing Wei, Miao Zhang, Chenglu Lin, Xi Wang
  • Patent number: 8623740
    Abstract: A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 7, 2014
    Assignee: Soitec
    Inventors: Didier Landru, Ionut Radu, Sébastien Vincent
  • Patent number: 8617962
    Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 31, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sebastien Kerdiles
  • Patent number: 8609511
    Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
  • Patent number: 8604545
    Abstract: Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Masaki Koyama, Motoki Nakashima
  • Patent number: 8603896
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 10, 2013
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8598013
    Abstract: To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Yoichi Iikubo, Yoshiaki Yamamoto, Kenichiro Makino
  • Publication number: 20130316488
    Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.
    Type: Application
    Filed: May 26, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoartabari, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8592291
    Abstract: A hexagonal boron nitride thin film is grown on a metal surface of a growth substrate and then annealed. The hexagonal boron nitride thin film is coated with a protective support layer and released from the metal surface. The boron nitride thin film together with the protective support layer can then be transferred to any of a variety of arbitrary substrates.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Yumeng Shi, Jing Kong, Christoph Hamsen, Lain-Jong Li
  • Publication number: 20130307031
    Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8586451
    Abstract: A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 19, 2013
    Assignee: STMicroelectronics S.R.L.
    Inventors: Vincenzo Vinciguerra, LuigiGiuseppe Occhipinti
  • Patent number: 8574929
    Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 5, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist
  • Patent number: 8551862
    Abstract: To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer 7 by forming a silicon film layer on a surface 4 of an insulating substrate 3 comprising the steps in the following order of: applying a surface activation treatment to both a surface 2 of a silicon wafer 1 or a silicon wafer 1 to which an oxide film is layered and a surface 4 of the insulating substrate 3 followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer 5 at a temperature of 200° C. to 350° C., and thinning the silicon wafer 1 by a combination of grinding, etching and polishing to form a silicon film layer.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
  • Patent number: 8541290
    Abstract: A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 106, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 24, 2013
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruce Faure
  • Patent number: 8536629
    Abstract: A method for manufacturing a semiconductor device, includes: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween. There can be provided a method capable of manufacturing a semiconductor device having high element density, high performance and high reliability, with high yield.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Hiromitsu Hada
  • Patent number: 8530332
    Abstract: An object is to provide an SOI substrate with excellent characteristics even in the case where a single crystal semiconductor substrate having crystal defects is used. Another object is to provide a semiconductor device using such an SOI substrate. A single crystal semiconductor layer is formed by an epitaxial growth method over a surface of a single crystal semiconductor substrate. The single crystal semiconductor layer is subjected to first thermal oxidation treatment to form a first oxide film. A surface of the first oxide film is irradiated with ions, whereby the ions are introduced to the single crystal semiconductor layer. The single crystal semiconductor layer and a base substrate are bonded with the first oxide film interposed therebetween. The single crystal semiconductor layer is divided at a region where the ions are introduced by performing thermal treatment, so that the single crystal semiconductor layer is partly left over the base substrate.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida, Takashi Shimazu
  • Patent number: 8530998
    Abstract: Methods and apparatus for producing a semiconductor on insulator structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis, wherein a liquidus viscosity of the glass substrate is about 100,000 Poise or greater.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: September 10, 2013
    Assignee: Corning Incorporated
    Inventors: Kishor Purushottam Gadkaree, Matthew John Dejneka, Adam James Ellison
  • Patent number: 8530333
    Abstract: An object is to provide a semiconductor device which solves a problem that can occur when a substrate having an insulating surface is used. The semiconductor device includes a base substrate having an insulating surface; a conductive layer over the insulating surface; an insulating layer over the conductive layer; a semiconductor layer having a channel formation region, a first impurity region, a second impurity region, and a third impurity region provided between the channel formation region and the second impurity region over the insulating layer; a gate insulating layer configured to cover the semiconductor layer; a gate electrode over the gate insulating layer; a first electrode electrically connected to the first impurity region; and a second electrode electrically connected to the second impurity region. The conductive layer is held at a given potential.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Hiromichi Godo, Satoshi Shinohara
  • Patent number: 8530336
    Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Nei, Akihisa Shimomura
  • Patent number: 8524574
    Abstract: A method for manufacturing a solid-state image device which includes the steps of: forming a silicon epitaxial growth layer on a silicon substrate; forming photoelectric conversion portions, transfer gates, and a peripheral circuit portion in and/or on the silicon epitaxial growth layer and further forming a wiring layer on the silicon epitaxial growth layer; forming a split layer in the silicon substrate at a side of the silicon epitaxial growth layer; forming a support substrate on the wiring layer; peeling the silicon substrate from the split layer so as to leave a silicon layer formed of a part of the silicon substrate at a side of the support substrate; and planarizing the surface of the silicon layer.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Sony Corporation
    Inventor: Chiaki Sakai
  • Patent number: 8518797
    Abstract: The method includes steps of adding first ions to a predetermined depth from a main surface of a semiconductor substrate by irradiation of the semiconductor substrate with a planar, linear, or rectangular ion beam, so that a separation layer is formed; adding second ions to part of the separation layer formed in the semiconductor substrate; disposing the main surface of the semiconductor substrate and a main surface of a base substrate to face each other in order to bond a surface of an insulating film and the base substrate; and cleaving the semiconductor substrate using the separation layer as a cleavage plane, so that a single crystal semiconductor layer is formed over the base substrate. The mass number of the second ions is the same as or larger than that of the first ions.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Shunpei Yamazaki
  • Publication number: 20130214423
    Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: SOITEC
    Inventor: Mariam Sadaka
  • Publication number: 20130217206
    Abstract: Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicone and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: RE45017
    Abstract: A porous Si layer is formed on a single-crystal Si substrate, and then a p+-type Si layer, p-type Si layer and n+-type Si layer which all make up a solar cell layer. After a protective film is made on the n+-type Si layer, the rear surface of the single-crystal Si substrate is bonded to a tool, and another tool is bonded to the front surface of the protective film. Theo, the tools are pulled in opposite directions to mechanically rupture the porous Si layer and to separate the solar cell layer from the single-crystal substrate. The solar cell layer is subsequently sandwiched between two plastic substrates to make a flexible thin-film solar cell.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 15, 2014
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Hiroshi Tayanaka