With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
  • Patent number: 8513092
    Abstract: A method for producing a stacked structure having an ultra thin buried oxide (UTBOX) layer therein by forming an electrical insulator layer on a donor substrate, introducing elements into the donor substrate through the insulator layer, forming an electrical insulator layer, on a second substrate, and bonding the two substrates together to form the stack, with the two insulator layers limiting the diffusion of water and forming the UTBOX layer between the two substrates at a thickness of less than 50 nm, wherein the donor oxide layer has, during bonding, a thickness at least equal to that of the bonding oxide layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 20, 2013
    Assignee: Soitec
    Inventor: Didier Landru
  • Patent number: 8507313
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Publication number: 20130203236
    Abstract: Methods for making growth templates for the epitaxial growth of compound semiconductors and other materials are provided. The growth templates are thin layers of single-crystalline materials that are themselves grown epitaxially on a substrate that includes a thin layer of sacrificial material. The thin layer of sacrificial material, which creates a coherent strain in the single-crystalline material as it is grown thereon, includes one or more suspended sections and one or more supported sections.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Inventors: Max G. Lagally, Deborah M. Paskiewicz, Boy Tanto
  • Patent number: 8497187
    Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 30, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Susumu Kuwabara
  • Patent number: 8486804
    Abstract: A semiconductor device including a first element including a photodiode and an amplifier circuit which amplifies output current of the photodiode, over a first insulating film; and a second element including a color filter and an overcoat layer over the color filter over a second insulating film is manufactured. The first element and the second element are attached to each other by bonding the first insulating film and the second insulating film with a bonding material. Further, the amplifier circuit is a current mirror circuit including a thin film transistor. Still further, a color film may be used instead of a color filter.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Yoshiaki Oikawa, Atsushi Hirose, Masayuki Sakakura
  • Patent number: 8486772
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
  • Patent number: 8481409
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: July 9, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 8481375
    Abstract: A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kenshi Tada
  • Patent number: 8482009
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
  • Patent number: 8476146
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8476147
    Abstract: A bond substrate is irradiated with ions, so that an embrittlement layer is formed, then, the bond substrate is bonded to a base substrate. Next, a part of a region of the bonded bond substrate is heated at a temperature higher than a temperature of the other part of the region of the bond substrate, or alternatively, a first heat treatment is performed on the bonded bond substrate as a whole at a first temperature; and a second heat treatment is performed on a part of a region of the bonded bond substrate at a second temperature higher than the first temperature, so that separation of the bond substrate proceeds from the part of the region of the bond substrate to the other part of the region of the bond substrate in the embrittlement layer. Accordingly, a semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoki Okuno, Hajime Tokunaga
  • Patent number: 8466041
    Abstract: Provided is a method for manufacturing a lamination type semiconductor integrated device that can simultaneously attain grinding force resistance during back side grinding of a semiconductor wafer, heat resistance during anisotropic dry etching and the like, chemical resistance during plating and etching, smooth debonding of a support substrate for processing at the end, and low adherend staining; the method comprises at least a step of back side grinding of a first semiconductor wafer having a device formed on its surface and a step of laminating by electrical bonding the first semiconductor wafer with a second semiconductor wafer having a device formed on its surface, wherein, at the time of back side grinding of the first semiconductor wafer, back of the first semiconductor wafer is ground after surface of formed device on the first semiconductor wafer is bonded to a support substrate for processing by using a pressure-sensitive silicone adhesive.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: June 18, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yasuyoshi Kuroda, Kazunori Kondo, Hideto Kato
  • Patent number: 8455331
    Abstract: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Shichi, Naoki Suzuki
  • Patent number: 8445358
    Abstract: An object of the present invention is to reduce the influence of a foreign substance adhering to a single crystalline semiconductor substrate and manufacture a semiconductor substrate with a high yield. Another object of the present invention is to manufacture, with a high yield, a semiconductor device which has stable characteristics. In the process of manufacturing a semiconductor substrate, when an embrittled region is to be formed in a single crystalline semiconductor substrate, the surface of the single crystalline semiconductor substrate is irradiated with hydrogen ions from oblique directions at multiple (at least two) different angles, thereby allowing the influence of a foreign substance adhering to the single crystalline semiconductor substrate to be reduced and allowing a semiconductor substrate including a uniform single crystalline semiconductor layer to be manufactured with a high yield.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 21, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Keiichi Sekiguchi
  • Publication number: 20130115753
    Abstract: A method of manufacturing a thin film-bonded substrate in which a high-quality gallium nitride (GaN) thin film can be transferred. The method includes implanting ions into a first GaN substrate from a Ga surface thereof and thereby forming a first ion implantation layer, bonding a first heterogeneous substrate onto the Ga surface of the first GaN substrate, cleaving the first GaN substrate along the first ion implantation layer and thereby leaving a second GaN substrate on the first heterogeneous substrate, implanting ions into the second GaN substrate from an N surface thereof and thereby forming a second ion implantation layer, bonding a second heterogeneous substrate onto the N surface of the second GaN substrate, and cleaving the second GaN substrate along the second ion implantation layer and thereby leaving a GaN thin film.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 9, 2013
    Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.
    Inventor: Samsung Corning Precision Materials Co., Ltd.
  • Publication number: 20130093059
    Abstract: A bonded substrate, the surface roughness of which is reduced, and a method of manufacturing the same. The bonded substrate includes a base substrate and an intermediate layer disposed on the base substrate. The intermediate layer has a greater bubble diffusivity than the base substrate. A thin film layer is bonded onto the intermediate layer, and has a different chemical composition from the base substrate.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 18, 2013
    Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.
    Inventor: Samsung Corning Precision Materials, Co., Ltd.
  • Publication number: 20130093063
    Abstract: A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 18, 2013
    Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.
    Inventor: Samsung Corning Precision Materials Co., Ltd.
  • Patent number: 8421076
    Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Patent number: 8420503
    Abstract: A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: April 16, 2013
    Assignee: Shin—Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Makoto Kawai, Atsuo Ito, Yoshihiro Kubota, Kouichi Tanaka, Yuji Tobisaka, Hiroshi Tamura
  • Publication number: 20130089967
    Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.
    Type: Application
    Filed: September 27, 2012
    Publication date: April 11, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: SHIN-ETSU CHEMICAL CO., LTD.
  • Patent number: 8415231
    Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Publication number: 20130082361
    Abstract: Provided are a method of manufacturing a flexible device and a flexible device manufactured thereby. The method of manufacturing a flexible device according to the present disclosure includes: fabricating a device on an upper silicon layer of a silicon-on-insulator (SOI) substrate comprising a lower silicon layer, an insulation layer and the upper silicon layer stacked sequentially; adhering a second silicon substrate to the upper silicon layer; removing the lower silicon layer; transferring the upper silicon layer with the device fabricated to a flexible substrate using the second silicon substrate; and stacking a passivation layer on the flexible substrate, wherein the device is located at a position of a neutral mechanical plane of the entire device as the passivation layer is stacked.
    Type: Application
    Filed: February 14, 2012
    Publication date: April 4, 2013
    Inventors: Keon Jae LEE, Kwyro Lee, Geon Tae Hwang, Donggu Im
  • Patent number: 8409366
    Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: April 2, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Masaaki Sakuta, Akihiro Hashimoto
  • Publication number: 20130075726
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Pascal Fornara
  • Patent number: 8404563
    Abstract: The embrittlement layer and the semiconductor layer remaining on the periphery of the semiconductor substrate after separation are selectively removed using a mixed solution containing a substance functioning as an oxidizer for oxidizing a semiconductor, a substance dissolving an oxide of a semiconductor, and a substance functioning as a decelerator of oxidization of a semiconductor and dissolution of an oxide of a semiconductor. Note that the semiconductor film is separated from the semiconductor substrate along an embrittlement layer that is formed in the semiconductor substrate by implantation of an H+ ion generated from a hydrogen gas with use of an ion implantation apparatus.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuya Hanaoka
  • Patent number: 8405090
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 8394703
    Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki
  • Patent number: 8394655
    Abstract: A photoelectric conversion device with an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The photoelectric conversion device includes a first unit cell including a first electrode, a first impurity semiconductor layer, a single crystal semiconductor layer, and a second impurity semiconductor layer; and a second unit cell including a third impurity semiconductor layer, a non-single-crystal semiconductor layer, a fourth impurity semiconductor layer, and a second electrode. The second and third impurity semiconductor layers are in contact with each other so that the first and second unit cells are connected in series, and an insulating layer is provided for a surface of the first electrode and bonded to a supporting substrate.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8389385
    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Publication number: 20130052799
    Abstract: In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal to 200° C. In addition, the semiconductor substrate is subjected to plasma treatment while the semiconductor substrate is kept at a temperature of higher than or equal to 100° C. and lower than or equal to 400° C. after the hydrogen ion addition treatment, whereby Si—H bonds which have low contribution to separation of the semiconductor thin film layer can be reduced while Si—H bonds which have high contribution to separation of the semiconductor thin film layer, which are generated by the hydrogen ion addition treatment, are kept.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 28, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hiroshi OHKI
  • Publication number: 20130049175
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Publication number: 20130049174
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Patent number: 8383491
    Abstract: A step of forming an insulating film over a semiconductor substrate and forming an embrittled region in the semiconductor substrate by irradiating the semiconductor substrate with accelerated ions through the insulating film; a step of disposing a surface of the semiconductor substrate and a surface of a base substrate opposite to each other and bonding the surface of the insulating film to the surface of the base substrate; a step of forming a semiconductor layer over the base substrate with the insulating film interposed therebetween by causing separation along the embrittled region by performing heat treatment after the surface of the insulating film and the surface of the base substrate are bonded to each other; a step of performing etching treatment on the semiconductor layer; a step of irradiating the semiconductor layer subjected to the etching treatment with a laser beam; and a step of irradiating the semiconductor layer irradiated with the laser beam with plasma.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8383487
    Abstract: Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor la
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihisa Shimomura, Junpei Momo, Motomu Kurata, Taiga Muraoka, Kosei Nei
  • Publication number: 20130040437
    Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.
    Type: Application
    Filed: October 17, 2012
    Publication date: February 14, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: SUMITOMO ELECTRIC INDUSTRIES, LTD.
  • Patent number: 8372733
    Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 12, 2013
    Assignees: Soitec, Commissariat à l'Énergie Atomique
    Inventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
  • Patent number: 8367517
    Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Yoshihiro Komatsu
  • Publication number: 20130026663
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Applicant: SOITEC
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Publication number: 20130023108
    Abstract: An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 24, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Yujiro SAKURADA, Hideki TSUYA, Makoto FURUNO, Miku FUJITA
  • Patent number: 8357586
    Abstract: Provided is a method for manufacturing an SOI wafer, which is capable of: efficiently removing an ion-implanted defect layer existing in an ion implanted layer in the vicinity of a peeled surface peeled by an ion implantation peeling method; ensuring the in-plane uniformity of a substrate; and also achieving cost reduction and higher throughput. The method for manufacturing an SOI wafer includes at least the steps of: bonding a silicon wafer with or without an oxide film onto a handle wafer to prepare a bonded substrate, wherein the silicon wafer has an ion implanted layer formed by implanting hydrogen ions and/or rare gas ions into the silicon wafer; peeling the silicon wafer along the ion implanted layer, thereby transferring the silicon wafer onto the handle wafer to produce a post-peeling SOI wafer; immersing the post-peeling SOI wafer in an aqueous ammonia-hydrogen peroxide solution; and performing a heat treatment at a temperature of 900° C.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 22, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuji Tobisaka, Hiroshi Tamura
  • Patent number: 8357589
    Abstract: A method for thinning a structure of at least two assembled wafers, where one of the wafers includes channels on its surface facing the other wafer. In order to cause thinning of the structure, a fluid is introduced into the channels in a supercritical state and the fluid is passed from the supercritical state into the gaseous state. The channels do not open to the outside of the structure, such that the method further includes forming at least one access opening to the channels from the outer surface of the structure and before introducing the fluid in the supercritical state.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: January 22, 2013
    Assignee: Soitec
    Inventor: Marcel Broekaart
  • Patent number: 8354330
    Abstract: The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 15, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Dawei He, Zhongjian Wang, Dawei Xu, Chao Xia, Zhaorui Song, Yuehui Yu
  • Patent number: 8349705
    Abstract: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Tatsuya Mizoi, Hidekazu Miyairi, Koichiro Tanaka
  • Patent number: 8349704
    Abstract: A bond substrate is irradiated with accelerated ions to form an embrittled region in the bond substrate; an insulating layer is formed over a surface of the bond substrate or a base substrate; the bond substrate and the base substrate are bonded to each other with the insulating layer interposed therebetween; a region in which the bond substrate and the base substrate are not bonded to each other and which is closed by the bond substrate and the base substrate is formed in parts of the bond substrate and the base substrate; the bond substrate is separated at the embrittled region by heat treatment; and a semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoki Okuno, Akihisa Shimomura, Hajime Tokunaga
  • Patent number: 8343849
    Abstract: To provide a technical means which is capable of increasing crystallinity and planarity of a single crystal semiconductor layer, crystal defects are reduced in such a manner that a single crystal semiconductor substrate, in which an insulating film is formed on its surface and an embrittlement region is formed in a region at a predetermined depth from the surface, and a supporting substrate are attached to each other with the insulating film interposed therebetween; the single crystal semiconductor substrate is separated in the embrittlement region by a heat treatment; a single crystal semiconductor layer is irradiated with laser light over the supporting substrate with the insulating film interposed therebetween; a surface of the single crystal semiconductor layer is etched; and a plasma treatment is performed on the surface of the single crystal semiconductor layer.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Publication number: 20120329242
    Abstract: A method suitable to reprocess a semiconductor substrate is provided. A semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer is provided in a peripheral portion of the semiconductor substrate is subjected to etching treatment for removing the insulating layer and to etching treatment for removing the damaged semiconductor region selectively with a non-damaged semiconductor region left using a mixed solution including nitric acid, a substance dissolving a semiconductor material included in the semiconductor substrate and oxidized by the nitric acid, a substance controlling a speed of oxidation of the semiconductor material and a speed of dissolution of the oxidized semiconductor material, and nitrous acid, in which the concentration of the nitrous acid is higher than or equal to 10 mg/l and lower than or equal to 1000 mg/l. Through these steps, the semiconductor substrate is reprocessed.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 27, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Shunsuke KIMURA
  • Patent number: 8338268
    Abstract: A transfer process for silicon nanomembranes (SiNM) may involve treating a recipient substrate with a polymer structural support. After treating the recipient substrate, a substrate containing the intended transferable devices may be brought in direct contact with the aforementioned polymer layer. The two substrates may then go through a Deep Reactive Ion Etch (DRIE) to remove at least a portion of the substrate containing the devices. Oxide may be selectively removed with a buffered oxide wet etch, leaving the transferred SiNM on the recipient substrate with the Underlying polymer layer.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Lumilant, Inc.
    Inventors: Mathew Joseph Zablocki, Ahmed Sharkawy, Dennis W. Prather
  • Patent number: 8324075
    Abstract: The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Cecile Aulnette, Khalid Radouane
  • Patent number: 8324077
    Abstract: To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor layer in order to improve mobility of the transistors in a semiconductor device. Plural kinds of transistors which are separated from a single-crystal semiconductor substrate and include single-crystal semiconductor layers bonded to a substrate having an insulating surface with a bonding layer interposed therebetween are provided over the same substrate. One of the transistors uses a single-crystal semiconductor layer as an active layer, to which tensile strain is applied. The other transistors use single-crystal semiconductor layers as active layers, to which compressive strain using part of heat shrink generated by heat treatment of the base substrate after bonding is applied.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshifumi Tanada
  • Patent number: 8314006
    Abstract: Provided is a method for manufacturing a bonded wafer with a good thin film over the entire substrate surface, especially in the vicinity of the lamination terminal point. The method for manufacturing a bonded wafer comprises at least the following steps of: forming an ion-implanted region by implanting a hydrogen ion or a rare gas ion, or the both types of ions from a surface of a first substrate which is a semiconductor substrate; subjecting at least one of an ion-implanted surface of the first substrate and a surface of a second substrate to be attached to a surface activation treatment; laminating the ion-implanted surface of the first substrate and the surface of the second substrate in an atmosphere with a humidity of 30% or less and/or a moisture content of 6 g/m3 or less; and a splitting the first substrate at the ion-implanted region so as to reduce thickness of the first substrate, thereby manufacturing a bonded wafer with a thin film on the second substrate.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: November 20, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yuji Tobisaka, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Shoji Akiyama, Hiroshi Tamura