With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
  • Patent number: 8314018
    Abstract: A first embrittlement layer is formed by doping a first single-crystal semiconductor substrate with a first ion; a second embrittlement layer is formed by doping a second single-crystal semiconductor substrate with a second ion; the first and second single-crystal semiconductor substrates are bonded to each other; the first single-crystal semiconductor film is formed over the second single-crystal semiconductor substrate by a first heat treatment; an insulating substrate is bonded over the first single-crystal semiconductor film; and the first and second single-crystal semiconductor films are formed over the insulating substrate by a second heat treatment. A dose of the first ion is higher than that of the second ion and a temperature of the first heat treatment is lower than that of the second heat treatment.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Naoki Okuno, Masaki Koyama, Yasuhiro Jinbo
  • Patent number: 8309431
    Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: November 13, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Nguyet-Phuong Nguyen, Ian Cayrefourcq, Christelle Lagahe-Blanchard, Konstantin Bourdelle, Aurélie Tauzin, Franck Fournel
  • Publication number: 20120280367
    Abstract: The invention relates to a method for manufacturing a semiconductor substrate by providing a seed support layer and a handle support layer, forming at least one semiconductor layer, in particular of a Group III/V-semiconductor material, over the seed support layer, wherein the at least one semiconductor layer is in a strained state, forming a bonding layer over the at least one semiconductor layer, forming a bonding layer over the handle support layer, and bonding the seed and handle substrates together to obtain a donor-handle compound, by direct bonding between the bonding layer of the seed substrate and the bonding layer of the handle substrate. At least one of the bonding layer of the seed substrate and the bonding layer of the handle substrate includes a silicon nitride.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 8, 2012
    Applicant: SOITEC
    Inventor: Morgane Logiou
  • Publication number: 20120280355
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Application
    Filed: December 27, 2010
    Publication date: November 8, 2012
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Shoji Akiyama
  • Publication number: 20120282757
    Abstract: A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 8, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuya KAKEHATA, Kazutaka KURIKI
  • Patent number: 8293620
    Abstract: A method of implanting atoms and/or ions into a substrate, including: a) a first implantation of ions or atoms at a first depth in the substrate, to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, to form at least one second implantation plane.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: October 23, 2012
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, S.O.I. TEC Silicon On Insulator Technologies
    Inventors: Thomas Signamarcheix, Chrystel Deguet, Frederic Mazen
  • Patent number: 8288249
    Abstract: Manufacturing cost of an SOI substrate is reduced. Yield of an SOI substrate is improved. A method for manufacturing an SOI substrate includes the steps of irradiating a single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate, bonding the single crystal semiconductor substrate to a base substrate with an insulating film therebetween, and separating the single crystal semiconductor substrate and the base substrate at the embrittled region to form a semiconductor layer over the base substrate with the insulating film therebetween. In the step of forming the embrittled region, ion species which are not mass-separated are used as the ions and a temperature of the single crystal semiconductor substrate is set to 250° C. or higher at the time of irradiation with the ions.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Hideto Ohnuma
  • Patent number: 8288245
    Abstract: An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Kazuya Hanaoka
  • Publication number: 20120256327
    Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.
    Type: Application
    Filed: July 26, 2011
    Publication date: October 11, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
  • Patent number: 8283238
    Abstract: A manufacturing method of a semiconductor device in which a space between semiconductor films transferred to a plurality of places can be made small. Transfer of a semiconductor film from a bond substrate to a base substrate is carried out a plurality of times. In the case where a semiconductor film transferred first and a semiconductor film transferred later are provided adjacently, the latter transfer is carried out using a bond substrate with its end portion partially removed. The width in a perpendicular direction to the bond substrate used for the later transfer, of the region of the bond substrate corresponding to the removed end portion is larger than the thickness of the semiconductor film which is transferred first.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 9, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Tatsuya Mizoi, Hidekazu Miyairi, Koichiro Tanaka
  • Patent number: 8278187
    Abstract: Disclosed is a method for reprocessing a semiconductor substrate which is by-produced in manufacturing a silicon-on-insulator substrate. The method includes: forming an embrittlement layer in a single crystal semiconductor substrate; bonding the single crystal semiconductor substrate with a base substrate having an insulating surface; and separating the single crystal semiconductor substrate along the embrittlement layer to give a silicon-on-insulator substrate and a semiconductor substrate to be reprocessed. The above steps provide, in the peripheral portion on the semiconductor substrate, a projection comprising the embrittlement layer and a single crystal semiconductor layer over the embrittlement layer. The method is characterized by an etching step to selectively remove the projection without etching a portion where the projection is absent, which allows the semiconductor substrate to be reused for the production of another silicon-on-insulator substrate.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuya Hanaoka
  • Patent number: 8278189
    Abstract: The present invention provides a method of thinning a wafer. First, a wafer is provided. The wafer includes an active surface, a back surface and a side surface. The active surface is disposed opposite to the back surface. The side surface is disposed between the active surface and the back surface and encompasses the peripheral of the wafer. Next, a protective structure is formed on the wafer to at least completely cover the side surface. Last, a thinning process is performed upon the wafer from the back surface.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 2, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Patent number: 8273636
    Abstract: Methods for forming semiconductor structures comprising a layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor-on-insulator (SeOI) structure can be formed by a method comprising:—providing a donor substrate having a first density of vacancy clusters;—providing an insulating layer; —transferring a thin layer from the donor substrate to a support substrate with the insulating layer thereon;—curing the transferred thin layer to reduce the first density of vacancy clusters to a second density; and being characterized in that the step of providing an insulating layer comprises providing an oxygen barrier layer to be in contact with the transferred thin layer, the oxygen barrier layer limiting diffusion of oxygen toward the thin layer during the curing.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: September 25, 2012
    Assignee: Soitec
    Inventors: Eric Neyret, Oleg Kononchuk
  • Patent number: 8268659
    Abstract: A method for manufacturing an edge emitting semiconductor laser chip, which has a carrier substrate, an interlayer arranged between the carrier substrate and a component structure of the edge emitting semiconductor laser chip. The interlayer is adapted to provide adhesion between the carrier substrate and the component structure. The component structure has an active zone provided for generating radiation.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: September 18, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Christoph Eichler, Volker Härle, Christian Rumbolz, Uwe Strauss
  • Patent number: 8268700
    Abstract: There is disclosed a method for manufacturing an SOI wafer comprising at least: implanting a hydrogen ion, a rare gas ion, or both the ions into a donor wafer formed of a silicon wafer or a silicon wafer having an oxide film formed on a surface thereof from a surface of the donor wafer, thereby forming an ion implanted layer; performing a plasma activation treatment with respect to at least one of an ion implanted surface of the donor wafer and a surface of a handle wafer, the surface of the handle wafer is to be bonded to the ion implanted surface; closely bonding these surfaces to each other; mechanically delaminating the donor wafer at the ion implanted layer as a boundary and thereby reducing a film thickness thereof to provide an SOI layer, and performing a heat treatment at 600 to 1000° C.; and polishing a surface of the SOI layer for 10 to 50 nm based on chemical mechanical polishing.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: September 18, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Publication number: 20120228761
    Abstract: A semiconductor device includes a first substrate and a second substrate being bonded to each other, a posterior interconnect layer interposed between the first and second substrates, a weld pad disposed in the posterior interconnect layer, and a first annular opening disposed in the first substrate. The device further includes a dielectric layer formed in the first opening, a via surrounded by the first annular opening, and an interconnect layer disposed in the via. The device also includes a conductive bump disposed on the interconnect layer and electrically connected to the weld pad through the interconnect layer.
    Type: Application
    Filed: October 27, 2011
    Publication date: September 13, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: MINWEI XI, HONG ZHU
  • Publication number: 20120228689
    Abstract: The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: SOITEC
    Inventors: Nicolas Daval, Cécile Aulnette, Bich-Yen Nguyen
  • Publication number: 20120228730
    Abstract: A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel off a silicon thin film from the bulk portion of single-crystal silicon along the hydrogen ion-implanted layer, thereby obtaining an SOI substrate having an SOI layer on the quartz substrate. A concave portion, such as a hole or a micro-flow passage, is formed on a surface of the quartz substrate of the SOI substrate thus obtained, so that processes required for a DNA chip or a microfluidic chip are applied. A silicon semiconductor element for the analysis/evaluation of a sample attached/held to this concave portion is formed in the SOI layer.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji AKIYAMA, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8263477
    Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Steven Koester, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8263478
    Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 at a dosage of 1.5×1017 atoms/cm2 or higher to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 and the low melting glass substrate 20 are bonded together. The bonded substrate is heated at relatively low temperature, 120° C. or higher and 250° C. or lower (below a melting point of the support substrate). Further, an external shock is applied to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the heat-treated bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that a semiconductor substrate can be fabricated.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Publication number: 20120225536
    Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Applicant: Raytheon Company
    Inventors: Ralph Korenstein, Mary K. Herndon, Chae Deok Lee
  • Patent number: 8258043
    Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: September 4, 2012
    Assignees: National University Corporation Tokyo University of Agriculture and Technology, Nissin Ion Equipment Co., Ltd.
    Inventors: Toshiyuki Sameshima, Yutaka Inouchi, Takeshi Matsumoto, Yuko Fujimoto
  • Publication number: 20120220102
    Abstract: A method of manufacturing semiconductor wafers, the method comprising providing a donor wafer comprising a semiconductor substrate; performing a lithography step and process the said donor wafer accordingly; and performing at least two layers transfer out of said donor wafer wherein each of said at least two layer had been effected by said process
    Type: Application
    Filed: November 22, 2010
    Publication date: August 30, 2012
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquest
  • Publication number: 20120211770
    Abstract: There are provided a semiconductor device of low cost and high quality, a combined substrate used for manufacturing the semiconductor device, and methods for manufacturing them. The method for manufacturing the semiconductor device includes the steps of: preparing a single-crystal semiconductor member; preparing a supporting base; connecting the supporting base and the single-crystal semiconductor member to each other through a connecting layer containing carbon; forming an epitaxial layer on a surface of the single-crystal semiconductor member; forming a semiconductor element using the epitaxial layer; separating the single-crystal semiconductor member from the supporting base by oxidizing and accordingly decomposing the connecting layer after the step of forming the semiconductor element; and dividing the single-crystal semiconductor member separated from the supporting base.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 23, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Hideto Tamaso
  • Publication number: 20120214291
    Abstract: A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 23, 2012
    Applicant: SOITEC
    Inventors: Fabrice Letertre, Carlos Mazure, Michael R. Krames, Melvin B. McLaurin, Nathan F. Gardner
  • Patent number: 8247309
    Abstract: In order to reduce and render uniform the surface roughness and variations in thickness of a layer after detachment (post-fracture) of a donor substrate, the mean temperature of the donor substrate during implantation thereof is controlled so as to be in the range 20° C. to 150° C. with a maximum temperature variation of less than 30° C.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 21, 2012
    Assignee: Soitec
    Inventors: Sébastien Cattet, Guillaume Cattet-Guerrini, legal representative, Lise Guerrini, legal representative, Nadia Ben Mohamed, Benjamin Scarfogliere
  • Publication number: 20120205661
    Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama
  • Publication number: 20120208348
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Hideki TSUYA, Masaharu NAGAI
  • Patent number: 8241996
    Abstract: A method and structures for manufacturing multi-layered substrates. The method includes providing a donor substrate, which has a first deflection characteristic. The donor substrate has a backside, a face, a cleave region, and a thickness of material defined between the cleave region and the face. The method includes bonding the face of the donor substrate to a face of the handle substrate. The method includes coupling a backing substrate to the backside of the donor substrate to form a multilayered structure. The backing substrate is adequate to cause the first deflection characteristic of the donor substrate to be reduced to a predetermined level. The predetermined level is a suitable deflection characteristic for the thickness of material to be transferred onto the face of a handle substrate.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 14, 2012
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Harry Robert Kirk, James Andrew Sullivan
  • Patent number: 8241998
    Abstract: The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that is higher than that of silicon dioxide and a capacitance that is substantially equivalent to that of a layer of silicon dioxide having a thickness of less than or equal to 30 nm.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: August 14, 2012
    Assignee: Soitec
    Inventor: Ian Cayrefourcq
  • Publication number: 20120199956
    Abstract: The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Inventors: Monique Lecomte, Pascal Guenard, Sophie Rigal, David Sotta, Fabienne Janin, Christelle Veytizou
  • Publication number: 20120193714
    Abstract: Disclosed is an SOI substrate which includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 2, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: MASAO OKIHARA
  • Publication number: 20120184084
    Abstract: An optical device layer (ODL) in an optical device wafer is transferred to a transfer substrate. The ODL is formed on the front side of an epitaxy substrate through a buffer layer. The ODL is partitioned by a plurality of crossing streets to define regions where a plurality of optical devices are formed. The transfer substrate is bonded to the front side of the ODL, and the epitaxy substrate is cut along crossing streets into a plurality of blocks. A laser beam is applied to the epitaxy substrate from the back side of the epitaxy substrate to the unit of the optical device wafer and the transfer substrate in the condition where the focal point of the laser beam is set in the buffer layer, thereby decomposing the buffer layer. The epitaxy substrate divided into the plurality of blocks is peeled off from the ODL.
    Type: Application
    Filed: December 20, 2011
    Publication date: July 19, 2012
    Applicant: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Yoko Nishino
  • Publication number: 20120184085
    Abstract: To suppress desorption of hydrogen ions with which a single crystal semiconductor substrate is irradiated. A method for manufacturing an SOI substrate includes the following steps: irradiating a semiconductor substrate with carbon ions; irradiating the semiconductor substrate with a hydrogen ion after the irradiation with the carbon ion so as to form an embrittled region in the semiconductor substrate; disposing a surface of the semiconductor substrate and a surface of a base substrate to face each other and to be in contact with each other so that the semiconductor substrate and the base substrate are bonded; and heating the semiconductor substrate and the base substrate which are bonded to each other and separating the semiconductor substrate along the embrittled region so that a semiconductor layer is formed over the base substrate.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 19, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Junichi KOEZUKA
  • Publication number: 20120181550
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 19, 2012
    Applicant: DENSO CORPORATION
    Inventors: Hiroaki FUJIBAYASHI, Masami Naito, Nobuyuki Ooya
  • Publication number: 20120178253
    Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 12, 2012
    Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
  • Patent number: 8216917
    Abstract: A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 1010/cm3 or a mean size of less than 500 nm, forming an oxide layer on either a donor or receiver substrate, implanting atomic species in the donor substrate to form a weakened zone in the epitaxial layer, bonding the donor and receiver substrates together, with the oxide layer present at the bonding interface, fracturing the donor substrate in the weakened zone to transfer a layer of the donor substrate to the receiver substrate with the transferred layer including the epitaxial layer, and recycling the remainder of the donor substrate to form a receiver substrate for fabrication of a second semiconductor on insulator type substrate.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: July 10, 2012
    Assignee: Soitec
    Inventor: Christophe Maleville
  • Patent number: 8216915
    Abstract: The semiconductor substrate provided with a groove portion is irradiated with ions so that an embrittled region is formed in the semiconductor substrate, the semiconductor substrate and a base substrate are bonded to each other with an insulating layer interposed therebetween and a space which is surrounded by the groove portion in the semiconductor substrate and the base substrate is formed, and heat treatment is performed to separate the semiconductor substrate at the embrittled region, so that the semiconductor layer is formed over the base substrate with the insulating layer interposed therebetween.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Tokunaga, Naoki Okuno
  • Publication number: 20120171843
    Abstract: Without sacrificial layer etching, a microstructure and a micromachine are manufactured. A separation layer 102 is formed over a substrate 101, and a layer 103 to be a movable electrode is formed over the separation layer 102. At an interface of the separation layer 102, the layer 103 to be a movable electrode is separated from the substrate. A layer 106 to be a fixed electrode is formed over another substrate 105. The layer 103 to be a movable electrode is fixed to the substrate 105 with the spacer layer 103 which is partially provided interposed therebetween, so that the layer 103 to be a movable electrode and a layer 106 to be a fixed electrode face each other.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 5, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Patent number: 8211780
    Abstract: Adhesion defects between a single crystal semiconductor layer and a support substrate are reduced to manufacture an SOI substrate achiving high bonding strength between the single crystal semiconductor layer and the support substrate.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: July 3, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8207045
    Abstract: An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Kazutaka Kuriki
  • Patent number: 8207046
    Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: June 26, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Shin Matsumoto, Yasumori Fukushima, Yutaka Takafuji
  • Patent number: 8202787
    Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: June 19, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
  • Publication number: 20120146108
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 14, 2012
    Inventors: Shu-Ming CHANG, Chien-Hui CHEN, Yen-Shih HO, Chien-Hung LIU, Ho-Yin YIU, Ying-Nan WEN
  • Patent number: 8198148
    Abstract: Provided is a method for manufacturing a semiconductor device. The method includes: providing a first substrate where an active layer is formed on a buried insulation layer; forming a gate insulation layer on the active layer; forming a gate electrode on the gate insulation layer; forming a source/drain region on the active layer at both sides of the gate electrode; exposing the buried insulation layer around a thin film transistor (TFT) including the gate electrode and the source/drain region; forming an under cut at the bottom of the TFT by partially removing the buried insulation layer; and transferring the TFT on a second substrate.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: June 12, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, Seung Youl Kang, In-Kyu You
  • Patent number: 8198173
    Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Kenichiro Makino, Yoichi Iikubo, Masaharu Nagai, Aiko Shiga
  • Patent number: 8193076
    Abstract: The present disclosure relates to methods and apparatuses template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin for releasing a thin semiconductor substrate from a reusable semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 5, 2012
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Sam Tone Tor, Karl-Josef Kramer
  • Patent number: 8193068
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOL substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Publication number: 20120135584
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Application
    Filed: September 1, 2010
    Publication date: May 31, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Publication number: 20120133028
    Abstract: A semiconductor structure includes a thin semiconductor layer fixed on an applicator or flexible support, the thin layer having an exposed surface characterized by fractured solid bridges spaced apart by cavities. A method of producing the thin layer of semiconductor material includes implanting ions into the semiconductor wafer to define a reference plane, where the ion dose is above a minimum dose, but below a critical dose so as to avoid degrading the wafer surface. The method further includes applying a thermal treatment to define a layer of microcavities and applying stress to free the thin layer from the wafer.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 31, 2012
    Inventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol