Abstract: In sophisticated metallization systems, air gaps may be formed on the basis of a self-aligned patterning regime during which the conductive cap material of metal lines may be protected by providing one or more materials, which may subsequently be removed. Consequently, the etch behavior and the electrical characteristics of metal lines during the self-aligned patterning regime may be individually adjusted.

Abstract: A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device that is adapted to improve the production yield. The method generally includes etching a semiconductor substrate to form a trench, filling the trench with a conductive material, separating the filled conductive material to form a plurality of gate patterns and a bit line contact region, and etching the substrate to define an isolation region.

Abstract: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.

Abstract: The objects of the present invention are to form MEMS structures of which stress is controlled while maintaining the performance of high-performance LSI, to integrate MEMS Structures and LSI on a single chip, to electrically and chemically protect the MEMS structure and to reduce the stress of the whole movable part of the MEMS structure. To achieve the above objects, a silicide film formable at a low temperature is used for the MEMS structure. The temperature at the silicide film deposition T1 is selected optionally with reference the heat treatment temperature T2 and the pseudo-crystallization temperature T3. T2, the temperature of manufacturing process after the silicide film deposition, is determined does not cause the degradation of the characteristics of the high-performance LSI indispensable. Thus, the residual stress of the MEMS structures may be controlled.

Abstract: After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

Abstract: A method for forming an air gap structure on a substrate is described. The method comprises forming a sacrificial layer on a substrate, wherein the sacrificial layer comprises a decomposable material that thermally decomposes at a thermal decomposition temperature above approximately 350 degrees C. Thereafter, a cap layer is formed on the sacrificial layer at a substrate temperature less than the thermal decomposition temperature of the sacrificial layer. The sacrificial layer is decomposed by performing a first exposure of the substrate to ultraviolet (UV) radiation and heating the substrate to a first temperature less than the thermal decomposition temperature of the sacrificial layer, and the decomposed sacrificial layer is removed through the cap layer. The cap layer is cured to cross-link the cap layer by performing a second exposure of the substrate to UV radiation and heating the substrate to a second temperature greater than the first temperature.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.

Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).

Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.

Abstract: A room temperature operation polycrystalline infrared responsive photodetector, manufactured by a process, comprising the steps of patterning vacuum-deposited material and dry-etching a photonic crystal structure with resonant coupling tuned to long wavelengths.

Abstract: A method for fabricating a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, forming a plurality of wiring trenches in the insulating film, forming a plurality of wirings in the plurality of wiring trenches, forming a resist mask having an opening for selectively exposing one of regions between the plurality of wirings, on the insulating film and the plurality of wirings, forming an air gap trench by removing the insulating film from the selectively exposed one of the regions between the plurality of wirings by etching using the resist mask, and forming an air gap in the air gap trench by depositing an inter-layer insulating film over the plurality of wirings after removal of the resist mask.

Abstract: A semiconductor device includes a damascene structure and an air gap embedded in the damascene dielectric layer. A method of manufacturing a semiconductor device includes depositing a metal barrier in advance as an etch stop, forming a copper damascene interconnect structure, forming an air gap, and depositing a photosensitive passivation material on the air gap.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

Abstract: A method of forming an air gap within a semiconductor structure by the steps of: (a) using a sacrificial polymer to occupy a space in a semiconductor structure; and (b) heating the semiconductor structure to decompose the sacrificial polymer leaving an air gap within the semiconductor structure, wherein the sacrificial polymer of step (a) is a copolymer of bis[3-(4-benzocyclobutenyl)]1,n (n=2-12) alkyldiol diacrylate (such as bis[3-(4-benzocyclobutenyl)]1,6 hexanediol diacrylate) and 1,3 bis 2[4-benzocyclobutenyl(ethenyl)]benzene. In addition, a semiconductor structure, having a sacrificial polymer positioned between conductor lines, wherein the sacrificial polymer is a copolymer of bis[3-(4-benzocyclobutenyl)]1,n (n=2-12)alkyldiol diacrylate and 1,3 bis 2[4-benzocyclobutenyl(ethenyl)]benzene.

Abstract: In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52. The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10. Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50. In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract: A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing method and improving manufacturing yields.

Abstract: The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a first etch process employing the hard mask pattern. A spacer is formed on sidewalls of the first trenches. Second trenches, having a depth deeper than that of the first trenches, are formed in the isolation region by performing a second etch process employing the hard mask pattern.

Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

Abstract: An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

Abstract: A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the source layer and the semiconductor substrate, and between the drain layer and the semiconductor substrate, respectively; and the hollow portion in absence between the semiconductor layer under the gate electrode and the semiconductor substrate.

Abstract: A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath and above line features in adjacent levels, and perforated between line features. The line levels contain conductive lines and an air-gap-containing dielectric. A solid dielectric bridge layer, containing conductive contacts and formed by filling in a perforated dielectric layer, is disposed over the collection of interspersed line and via levels.

Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) device includes a number of steps. Initially, a first wafer is provided. Next, a bonding layer is formed on a first surface of the first wafer. Then, a portion of the bonding layer is removed to provide a cavity including a plurality of spaced support pedestals within the cavity. Next, a second wafer is bonded to at least a portion of the bonding layer. A portion of the second wafer provides a diaphragm over the cavity and the support pedestals support the diaphragm during processing. The second wafer is then etched to release the diaphragm from the support pedestals.

Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

Abstract: The semiconductor device having an air gap includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A metal line is formed to fill the metal line forming region of the insulation layer. An air gap is formed between the insulation layer and the metal line.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first die. A second plurality of trenches having a second orientation are formed in a second die. The second orientation is different from the first orientation.

Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Abstract: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

Abstract: This patent relates to a method of fabricating a semiconductor device. Gate insulating layer patterns and gate electrode layer patterns may be formed over a semiconductor substrate. A photoresist pattern through which part of a region between the gate electrode layer patterns is exposed may be formed over the semiconductor substrate including the gate electrode layer patterns. A passivation film, having an etch rate slower than that of the semiconductor substrate, may be formed on the photoresist pattern. A first trench may be formed in the semiconductor substrate using an etch process by employing the passivation film and the photoresist pattern as an etch mask. An ion implantation process may be performed on the semiconductor substrate in which the first trench is formed.

Abstract: The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.

Abstract: A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.

Abstract: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

Abstract: A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit device, comprising: at least one interconnect comprising one or more sidewalls; an interconnect sidewall spacer element arranged to provide structural support to the interconnect and formed on at least one of the interconnect sidewalls; and at least one void adjacent said interconnect and extending from the sidewall spacer element.

Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.