Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

Abstract: Provided are a method of growing carbon nanotubes laterally, including forming catalyst dots to grow carbon nanotubes on a substrate, forming a sacrificial layer including a plurality of nanochannels including regions having the catalyst dots formed therein, and growing carbon nanotubes through the nanochannels, and a field effect transistor using the method.

Abstract: An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: There is provided a method of manufacturing a substrate for flip chip, and a substrate for flip chip manufactured using the same. The method includes providing a base substrate including at least one conductive pad, forming a solder resist layer on the base substrate, the solder resist layer including a first opening exposing the conductive pad, forming a dry film on the solder resist layer, the dry film including a second opening connected with the first opening, forming a metal post in the first opening and a part of the second opening, filling the second opening above the metal post with solder paste, forming a solder cap by performing a reflow process on the filled solder paste, planarizing a surface of the solder cap, and removing the dry film. Accordingly, fine pitches and improve reliability can be achieved.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.

Abstract: Disclosed herein is an extendable network structure, which includes a first device portion, a second device portion and at least three connectors. The three connectors are connected to the first device portion. The second device portion is electrically connected to the first device portion through one of the three connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be extendable from an initial state to an extended state, such that a first distance between the first and second centers in the extended state is at least 1.1 fold of a second distance between the first and second centers in the initial state.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.

Abstract: A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect.

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Abstract: The invention discloses an array substrate, an LCD device, and a method for manufacturing the array substrate. The array substrate comprises scan line(s) and data line(s); the width of data line at the junction of the data line and the scan line is more than the width of the rest part of the data line. The invention can improve the final passed yield of LCD devices on the premise of not adding additional processes, and has the advantages of simple technology and low cost.

Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract: A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.

Abstract: The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.

Abstract: A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process.

Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.

Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.

Abstract: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

Abstract: Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.

Abstract: During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. In one embodiment, a semiconductor device is provided that includes a metallization system formed above a substrate. The metallization system includes a metal line formed in a dielectric layer and having a top surface. The metallization system also includes a conductive cap layer formed on the top surface. A via extends through the conductive cap layer and connects to the top surface of the metal line. A conductive barrier layer is formed on sidewalls of the via. An interface layer is formed of a noble metal between the conductive cap layer and the conductive barrier layer and between the top surface of the metal line and the conductive barrier layer.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.

Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.

Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Abstract: The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.

Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

Abstract: A method of forming a high density structure may include the steps of providing a substrate wherein the high density structure is to be formed with a release liner, the release liner being self-removable; forming at least one cavity in the substrate through the release liner, the at least one cavity forming at least a part of the high density structure; at least partially filling the at least one cavity with a filler material; sintering the thus formed structure; and removing the release liner from the substrate.

Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.