Interconnections, Comprising Conductors And Dielectrics, For Carrying Current Between Separate Components Within Device (epo) Patents (Class 257/E21.575)

  • Patent number: 8470654
    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Brent Gilgen
  • Patent number: 8471387
    Abstract: Disclosed herein is an extendable network structure, which includes a first device portion, a second device portion and at least three connectors. The three connectors are connected to the first device portion. The second device portion is electrically connected to the first device portion through one of the three connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be extendable from an initial state to an extended state, such that a first distance between the first and second centers in the extended state is at least 1.1 fold of a second distance between the first and second centers in the initial state.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 25, 2013
    Assignee: Monolithe Semiconductor Inc.
    Inventor: Kevin T. Y. Huang
  • Publication number: 20130154101
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.
    Type: Application
    Filed: June 4, 2012
    Publication date: June 20, 2013
    Applicant: SK Hynix Inc.
    Inventor: Dae Sik PARK
  • Patent number: 8466518
    Abstract: A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomoyuki Kirimura
  • Patent number: 8460967
    Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 11, 2013
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Publication number: 20130140579
    Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: THE BOEING COMPANY
    Inventors: Hasan Sharifi, Alexandros D. Margomenos, Ara K. Kurdoghlian, Miroslav Micovic, Keisuke Shinohara, Colleen M. Butler
  • Publication number: 20130140712
    Abstract: The invention discloses an array substrate, an LCD device, and a method for manufacturing the array substrate. The array substrate comprises scan line(s) and data line(s); the width of data line at the junction of the data line and the scan line is more than the width of the rest part of the data line. The invention can improve the final passed yield of LCD devices on the premise of not adding additional processes, and has the advantages of simple technology and low cost.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 6, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hungjui Chen
  • Patent number: 8455978
    Abstract: A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: June 4, 2013
    Inventor: Sang-Yun Lee
  • Patent number: 8456013
    Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: June 4, 2013
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Patent number: 8456009
    Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20130134601
    Abstract: The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hung-Hsiang Cheng, Tzu-Chih Lin, Chang-Ying Hung, Chih-Wei Wu
  • Publication number: 20130134558
    Abstract: A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Robert K. Speck, Kenneth B. Tull, Marjorie L. Miller
  • Patent number: 8450854
    Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Shyng-Tsong Chen
  • Publication number: 20130127031
    Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
  • Publication number: 20130126817
    Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 23, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Chih-Chao Yang
  • Patent number: 8445382
    Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: May 21, 2013
    Assignee: NXP B.V.
    Inventor: Willem Frederik Adrianus Besling
  • Publication number: 20130121055
    Abstract: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu Cheng HUANG, Hsin-Hsin KO, Jung-Hsuan CHEN, Chiting CHENG
  • Publication number: 20130113068
    Abstract: A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.
    Type: Application
    Filed: August 17, 2012
    Publication date: May 9, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Shiqun Gu
  • Publication number: 20130113092
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 9, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 8436404
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
  • Publication number: 20130109167
    Abstract: Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JOSEPHINE B. CHANG, ISAAC LAUER, CHUNG-HSUN LIN, JEFFREY W. SLEIGHT
  • Publication number: 20130105996
    Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Applicants: ZEON CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Robert L. Bruce, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura
  • Patent number: 8432035
    Abstract: During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. In one embodiment, a semiconductor device is provided that includes a metallization system formed above a substrate. The metallization system includes a metal line formed in a dielectric layer and having a top surface. The metallization system also includes a conductive cap layer formed on the top surface. A via extends through the conductive cap layer and connects to the top surface of the metal line. A conductive barrier layer is formed on sidewalls of the via. An interface layer is formed of a noble metal between the conductive cap layer and the conductive barrier layer and between the top surface of the metal line and the conductive barrier layer.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: April 30, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Volker Kahlert, Christof Streck
  • Patent number: 8431446
    Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 30, 2013
    Assignee: MicronTechnology, Inc
    Inventor: Stephen Tang
  • Patent number: 8432040
    Abstract: An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Shih Yeh
  • Publication number: 20130099352
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng
  • Publication number: 20130099386
    Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.
    Type: Application
    Filed: August 29, 2012
    Publication date: April 25, 2013
    Inventor: Jang Uk LEE
  • Patent number: 8426299
    Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Joon-Sung Kim, Hye-Soo Shin, Mi-Youn Kim, Young-Soo Kim
  • Patent number: 8426938
    Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Jun Park, Yong Woo Lee, Chang Rok Moon
  • Patent number: 8426941
    Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Sakurai, Satoshi Goto, Toru Fujioka
  • Publication number: 20130093052
    Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Yu MA, Kuo-Ji CHEN, Fang-Tsun CHU, Ta-Pen GUO
  • Publication number: 20130093069
    Abstract: The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 18, 2013
    Applicant: CYNTEC CO., LTD.
    Inventors: BAU-RU LU, JENG-JEN LI, CHIANG KAIPENG
  • Publication number: 20130093045
    Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiu-Ying Cho
  • Patent number: 8421230
    Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 16, 2013
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Didier Louis, Jean Du Port De Poncharra
  • Patent number: 8415803
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • Patent number: 8415790
    Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 9, 2013
    Assignee: Advance Semiconductor Engineering, Inc.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 8415248
    Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Qinghuang Lin, Sampath Purushothaman, Terry A. Spooner, Shawn M. Walsh
  • Patent number: 8415246
    Abstract: A method of forming a high density structure may include the steps of providing a substrate wherein the high density structure is to be formed with a release liner, the release liner being self-removable; forming at least one cavity in the substrate through the release liner, the at least one cavity forming at least a part of the high density structure; at least partially filling the at least one cavity with a filler material; sintering the thus formed structure; and removing the release liner from the substrate.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: April 9, 2013
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Jeroen van den Brand, Andreas Heinrich Dietzel
  • Patent number: 8415238
    Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
  • Publication number: 20130082347
    Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Applicant: Broadcom Corporation
    Inventors: Xiangdong CHEN, Wei Xia
  • Publication number: 20130084700
    Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 4, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Patent number: 8409987
    Abstract: Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Mirko Glass, Raashina Humayun, Michal Danek, Kaihan Ashtiani, Feng Chen, Lana Hiului Chan, Anil Mane
  • Patent number: 8409901
    Abstract: Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: April 2, 2013
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Mourad El-Gamal, Dominique Lemoine, Paul-Vahe Cicek, Frederic Nabki
  • Patent number: 8409924
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M Chrysler, Devendra Natekar
  • Publication number: 20130078802
    Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 28, 2013
    Inventors: Kazuhiko FUSE, Shinichi KATO
  • Publication number: 20130075907
    Abstract: In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: Broadcom Corporation
    Inventor: Mengzhi PANG
  • Patent number: 8404593
    Abstract: In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwon Hong, GeumJung Seong, Jongmyeong Lee, Hyunbae Lee, Bonghyun Choi
  • Patent number: 8405206
    Abstract: A semiconductor module includes a module housing, at least one substrate, a number N of at least two controllable power semiconductor chips arranged inside the module housing and one after another in a lateral direction, a single main load terminal arranged outside the module housing and electrically connected to the first main electrodes, and an auxiliary terminal arranged outside the module housing and electrically connected to the first main electrodes via an auxiliary terminal connecting conductor.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thomas Duetemeyer, Thomas Auer, Georg Braeker, Ronny Herms
  • Patent number: 8404523
    Abstract: A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 26, 2013
    Assignee: Micron Technoloy, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8399308
    Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song