By Forming Via Holes (epo) Patents (Class 257/E21.577)
  • Patent number: 11232986
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 25, 2022
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Patent number: 11232977
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 25, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • Patent number: 11164816
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a first lattice constant, a first word line positioned in the substrate, and a plurality of stress regions positioned adjacent to lower portions of sidewalls of the first word line. The plurality of stress regions have a second lattice constant, the second lattice constant of the plurality of stress regions is different from the first lattice constant of the substrate.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11133247
    Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 11043465
    Abstract: A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773° C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as tI, and a thickness of each of the metal layers being denoted as tM, a value of tI/tM is greater than or equal to 4.3.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 22, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Notsu, Hisato Michikoshi
  • Patent number: 11023647
    Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
  • Patent number: 10957640
    Abstract: A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the conductive structure. The dielectric layer has a plurality of through holes therein, and at least one of the through holes exposes the conductive structure. The conductive features are respectively present in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Patent number: 10930548
    Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
  • Patent number: 10872808
    Abstract: An etch stop layer is formed on a lower wiring. An interlayer insulating film covers the lower wiring and the etch stop layer. A via exposes an upper surface of the etch stop layer, in the interlayer insulating film. A first filler is formed in the via. The first filler is etched to a first filler pattern. A second filler is formed on the first filler pattern and is etched to a second filler pattern. A trench is formed by etching the interlayer insulating film. The first and second filler patterns are etched during the forming of the trench to form a residual filler pattern. The residual filler pattern and the etch stop layer are removed and a wiring structure is formed electrically connected to the lower wiring. The via includes lower and upper portions and the trench includes the upper portion of the via.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS., LTD.
    Inventors: Jin Ho Park, Sae Il Son, Hye Jun Jin, Yun-Won Ha
  • Patent number: 10861742
    Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • Patent number: 10847412
    Abstract: A method for manufacturing an interconnect structure with air gaps includes the following steps. A substrate including a first insulating layer formed thereon is provided. Plural conductive lines are formed in the first insulating layer. A patterned hard mask is formed on the first insulating layer and the conductive lines and exposes portions of the first insulating layer and portions of the conductive lines. The exposed portions of the first insulating layer are then removed to form a plurality of recesses in the first insulating layer. After that, a second insulating layer and a third insulating layer are formed in the recesses to seal the recesses and to form a plurality of air gaps in the recesses. At least two air gaps are respectively formed at two sides of one conductive line of the plurality of conductive lines. A via structure is then formed on the one conductive line.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10833017
    Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: November 10, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yanxiang Liu, Haining Yang, Youseok Suh, Jihong Choi, Junjing Bao
  • Patent number: 10756036
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 25, 2020
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: John Moore, Joseph F. Brooks
  • Patent number: 10748767
    Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 10714361
    Abstract: A method of fabricating semiconductor packages includes forming an insulating polymer layer on a substrate to cover a plurality of conductive patterns on the substrate, planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member, and patterning the planarized insulating polymer layer to expose at least parts of the plurality of conductive patterns.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 14, 2020
    Assignee: FOUNDATION FOR RESEARCH AND BUSINESS, SEOUL NATIONAL UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Sung Dong Kim, Ju Hwan Jung
  • Patent number: 10714329
    Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Ting Lin, Chen-Yuan Kao, Rueijer Lin, Yu-Sheng Wang, I-Li Chen, Hong-Ming Wu
  • Patent number: 10707166
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which one or more interconnect structures are to be formed includes depositing a dielectric layer and forming a trench for each interconnect structure to be formed in the metallization layer. An insulating liner layer is deposited that serves both as a metal diffusion barrier and as a metal adhesion layer for the interconnect structures.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10707239
    Abstract: A wiring having excellent electrical characteristics is provided. A wiring having stable electrical characteristics is provided. A device is manufactured through the steps of forming a first insulating film over a substrate, forming a second insulating film over the first insulating film, removing part of the first insulating film and part of the second insulating film to form a first opening, forming a first conductor in the first opening and over a top surface of the second insulating film, and forming a second conductor by planarizing a surface of the first conductor so as to remove part of the first conductor.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Tomoaki Moriwaka
  • Patent number: 10658287
    Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10566314
    Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10535566
    Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu
  • Patent number: 10529554
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10504780
    Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 10396091
    Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes, a first semiconductor layer, a gate insulating layer, a first contact, a second semiconductor layer, a second contact, and a first conductive layer. The control gate electrodes are stacked above a substrate. The first semiconductor layer faces the control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. The first contact is connected to an upper end of the first semiconductor layer. The second contact is connected to a lower end of the first semiconductor layer via the second semiconductor layer. The first conductive layer is provided above the second contact. Moreover, an end of the first conductive layer closest to the first contact is closer to the first contact than an end of the second contact closest to the first contact.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kei Sakamoto
  • Patent number: 10388645
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
  • Patent number: 10340218
    Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Patent number: 10283496
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
  • Patent number: 10283608
    Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank Mont, Mark Raymond, Chengyu Niu
  • Patent number: 10282487
    Abstract: A mask data generation method includes obtaining data of a pattern including a plurality of pattern elements, dividing a region of the pattern into a plurality of sections so that each pattern element is arranged in each section by using the obtained data of the pattern and generating map data including information indicative of presence or absence of the pattern element in each section, setting one piece of mask individual information out of a plurality pieces of mask individual information for each section including the pattern element by using a constraint condition, which inhibits setting of same mask individual information in a constraint region including one section and surrounding sections thereof, and the map data, and generating the data of the plurality of masks corresponding to the plurality pieces of mask individual information by using the set mask individual information.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: May 7, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadashi Arai
  • Patent number: 10270415
    Abstract: A receiving coupler for large diameter capacitive data links comprises at least two layers of isolating material, having different lengths and being attached to each other. The shorter layer comprises on its outer surface a first pair of conductors, whereas the longer layer comprises a second pair and a third pair of conductors. The conductors are connected to each other by vias. The stack of layers of different lengths can be adapted to various curve radii of transmitting components of a capacitive rotary joint.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 23, 2019
    Assignee: SCHLEIFRING GMBH
    Inventors: Herbert Weithmann, Holger Steffens, Michael Tekloth
  • Patent number: 10262868
    Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Yi Jiang, Juan Boon Tan, Zhehui Wang
  • Patent number: 10217725
    Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10211093
    Abstract: An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The interconnect includes a first single-damascene interconnect line disposed in a first interlayer dielectric layer, and a non-damascene via on the first single-damascene interconnect line that may be formed from cobalt, titanium and/or tungsten. A first SiCN layer may be formed on one or more sidewalls of the non-damascene via. A second single-damascene layer may be formed on the non-damascene via in which the second single-damascene layer may be disposed in a second interlayer dielectric layer. A second SiCN layer may be formed on at least part of an upper surface of the first single-damascene layer, and a third SiCN layer may be formed on at least part of an upper surface of the second single-damascene layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Don Lee, Daniel Sawyer, Steven English
  • Patent number: 10204758
    Abstract: The present invention discloses a positive and negative ion source based on radio-frequency inductively coupled discharge, comprising a tube, a middle portion of which is communicated with an intake pipe; discharge coils electrically connected to a matched network and a radio-frequency power supply successively are wound on the tube; one end of the tube is connected to a first cover plate in a sealed manner, and the first cover plate is connected with a positive ion extraction gate via an insulating medium; the positive ion extraction gate is electrically connected to a negative pole of a DC power supply; the other end of the tube is connected to a second cover plate in a sealed manner, the second cover plate is connected to a third cover plate in a sealed manner via a sidewall, and the third cover plate is connected with a negative ion extraction gate via an insulating medium; and the negative ion extraction gate is electrically connected to a positive pole of the DC power supply.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: February 12, 2019
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Fei Gao, Younian Wang
  • Patent number: 10204866
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 12, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 10192815
    Abstract: A wiring board includes: a first insulating layer; a first wiring layer formed on a lower surface of the first insulating layer; a first through hole which penetrates the first insulating layer; a first via wiring including: a filling portion formed to fill the first through hole; and a protruding portion protruding upward from an upper surface of the first insulating layer; a second wiring layer including a land, wherein the land includes an outer circumferential portion and a central portion, a second insulating layer formed on the upper surface of the first insulating layer; a second through hole which penetrates the second insulating layer in the thickness direction; a second via wiring formed to fill the second through hole; and a third wiring layer formed on an upper surface of the second insulating layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 29, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kosuke Tsukamoto, Noriyoshi Shimizu
  • Patent number: 10163707
    Abstract: Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hong Chang, Hsin-Chih Lin, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
  • Patent number: 10163794
    Abstract: The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chun Wang, Su-Jen Sung
  • Patent number: 10164035
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Kai-Yu Cheng
  • Patent number: 10141339
    Abstract: Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10134762
    Abstract: Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10090321
    Abstract: An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. A level difference is formed in a side surface of the contact, a portion of a region of the side surface other than the level difference contacts the insulating film. The insulating member contacts the level difference.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shingo Nakajima
  • Patent number: 10074672
    Abstract: A wiring having excellent electrical characteristics is provided. A wiring having stable electrical characteristics is provided. A device is manufactured through the steps of forming a first insulating film over a substrate, forming a second insulating film over the first insulating film, removing part of the first insulating film and part of the second insulating film to form a first opening, forming a first conductor in the first opening and over a top surface of the second insulating film, and forming a second conductor by planarizing a surface of the first conductor so as to remove part of the first conductor.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Tomoaki Moriwaka
  • Patent number: 9991157
    Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 5, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 9953863
    Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Te Ho, Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 9922930
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 9917106
    Abstract: Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chi-Chun Liu
  • Patent number: 9905751
    Abstract: A method includes patterning a metal layer to form a plurality of bottom electrode features, forming a Magnetic Tunnel Junction (MTJ) stack by a line-of-sight deposition process such that a first portion of the MTJ stack is formed on the bottom electrode features, and a second portion of the MTJ stack is formed on a level that is different than a top surface of the bottom electrode features, and performing a removal process to remove the second portion of the MTJ stack while leaving the first portion of the MTJ stack substantially intact.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Harry-Hak-Lay Chuang, Ru-Liang Lee
  • Patent number: 9870898
    Abstract: A plasma processing method includes applying a pulse wave of high frequency electric power for plasma generation and a pulse wave of high frequency electric power for bias whose frequency is lower than that of the high frequency electric power for plasma generation on the mounting table; and controlling the pulse wave of the high frequency electric power for plasma generation and the pulse wave of the high frequency electric power for bias such that a predetermined phase difference is generated between the pulse wave of the high frequency electric power for plasma generation and the pulse wave of the high frequency electric power for bias, and a duty ratio of the high frequency electric power for plasma generation becomes greater than or equal to a duty ratio of the high frequency electric power for bias.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 16, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masafumi Urakawa, Koichi Nagami
  • Patent number: 9859328
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao