By Selective Deposition Of Conductive Material In Vias, E.g., Selective Chemical Vapor Deposition On Semiconductor Material, Plating (epo) Patents (Class 257/E21.586)
  • Patent number: 10566211
    Abstract: Methods for etching tungsten and other metal or metal-containing films using a nitrogen-containing etchant gas are provided. The methods involve exposing the film to a continuous wave (CW) plasma and switching to a pulsed plasma toward the end of the etching operation. The pulsed plasma has a lower concentration of nitrogen radicals and can mitigate the effects of nitridation on the tungsten surface. In some embodiments, subsequent deposition on etched surfaces is performed with no nucleation delay. Apparatuses for performing the methods are also provided.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 18, 2020
    Assignee: Lam Research Corporation
    Inventors: Anand Chandrashekar, Madhu Santosh Kumar Mutyala
  • Patent number: 10512166
    Abstract: A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 17, 2019
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Lian Cheng
  • Patent number: 10490629
    Abstract: A method for forming power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Dae Sub Jung, Bo Liu, Roger To-Hoi Szeto
  • Patent number: 10453737
    Abstract: A method is described for void-free material filling of fine recessed features found in semiconductor devices. According to one embodiment, the method includes providing a patterned substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, coating the substrate with a metal-containing catalyst layer, deactivating a portion of the metal-containing catalyst layer that is near the opening of the recessed feature by exposure to a halogen-containing gas, and selectively depositing a material on the metal-containing catalyst layer in the recessed feature that has not been deactivated by the halogen-containing gas. The method can further include repeating the coating, deactivating and selectively depositing at least once to deposit an additional amount of the material to fully fill the recessed feature.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 10115790
    Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 30, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Steve M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
  • Patent number: 10084130
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 25, 2018
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Jun Liu, Kristy A. Campbell
  • Patent number: 9947621
    Abstract: A copper or copper alloy is formed in a reflow enhancement layer lined opening present in an interconnect dielectric material layer. A ruthenium (Ru) or osmium (Os) doped copper or copper alloy cap is then formed via ion implantation and annealing in an upper portion of a copper or copper alloy present in the opening. The upper portion of the copper or copper alloy containing the ruthenium (Ru) or osmium (Os) doped copper or copper alloy cap can mitigate or even present prevent preferential loss of copper which can aid in lowering the interconnect resistance of the structure.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9892957
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 9824918
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ming Zhou
  • Patent number: 9819076
    Abstract: The present invention relates to a method for manufacturing an internal antenna (intenna) and, in particular, to a method for manufacturing an intenna, which allows a resin molded product to be smoothly and securely plated with a metal by applying a primer paint on the surface of the resin molded product, and thereby improves the reliability of the metal plating formed on the resin molded product.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: November 14, 2017
    Assignees: INTOPS.CO., LTD.
    Inventor: Bon-sool Koo
  • Patent number: 9812355
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having an insulating film and a plurality of conductive films on a surface; reducing the substrate by supplying a first reducing gas to the substrate so that at least one of a plurality of process conditions of the first reducing gas is controlled so that a product of a plurality of process conditions becomes a predetermined value, wherein the process conditions of the first reducing gas include a partial pressure of the first reducing gas in a region where the substrate exists and a time taken to supply the first reducing gas to the substrate corresponding to a temperature of the first reducing gas; and selectively forming a metal film on the plurality of the reduced conductive films by supplying a second reducing gas and a metal-containing gas to the substrate.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 7, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kimihiko Nakatani, Hiroshi Ashihara
  • Patent number: 9786593
    Abstract: A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 10, 2017
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 9758865
    Abstract: The present disclosure provides a silicon film forming method for forming a silicon film on a workpiece having a processed surface, including: forming a seed layer by supplying a high-order aminosilane-based gas containing two or more silicon atoms in a molecular formula onto the processed surface and by having silicon adsorbed onto the processed surface; and forming a silicon film by supplying a silane-based gas not containing an amino group onto the seed layer and by depositing silicon onto the seed layer, wherein, when forming a seed layer, a process temperature is set within a range of 350 degrees C. or lower and a room temperature or higher.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 12, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Kazuya Takahashi, Katsuhiko Komori, Yoshikazu Furusawa, Mitsuhiro Okada, Hiroyuki Hayashi, Akinobu Kakimoto
  • Patent number: 9685316
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 9589894
    Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel Edelstein, Takeshi Nogami, Christopher Parks, Tsong Lin Leo Tai
  • Patent number: 9041210
    Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Jessica A. Levy, Cameron E. Luce, Daniel S. Vanslette, Bucknell C. Webb
  • Patent number: 9034761
    Abstract: Disclosed are metal-containing precursors having the formula Compound (I) wherein: —M is a metal selected from Ni, Co, Mn, Pd; and —each of R-1, R2, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H; a C1-C4 linear, branched, or cyclic alkyl group; a C1-C4 linear, branched, or cyclic alkylsilyl group (mono, bis, or tris alkyl); a C1-C4 linear, branched, or cyclic alkylamino group; or a C1-C4 linear, branched, or cyclic fluoroalkyl group. Also disclosed are methods of synthesizing and using the disclosed metal-containing precursors to deposit metal-containing films on a substrate via a vapor deposition process.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignees: L'Air Liquide, SociétéAnonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, American Air Liquide, Inc.
    Inventors: Clément Lansalot-Matras, Andrey V. Korolev
  • Patent number: 9018096
    Abstract: A method of manufacturing a structure comprising substantially planar electronic devices comprises providing an active material layer having a plurality of insulative features formed therein. The features at least partly inhibit electrical current flow and define at least a first substantially planar electronic device in the layer having at least first and second terminals comprising an area of the active material layer. A patterned dielectric layer having an exposed surface patterned with at least a first depression arranged over the first terminal is formed over the active material layer. Dielectric material is removed from at least a base of the first depression to expose a first terminal surface and form a hole through the dielectric material to the first terminal. The hole is at least partly filled with electrically conductive material to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Pragmatic Printing Ltd.
    Inventors: Richard David Price, Ian Barton
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8921225
    Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
  • Patent number: 8906790
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Patent number: 8906805
    Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Woon-kyung Lee, Jin-taek Park
  • Patent number: 8890262
    Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vimal Kamineni, Ruilong Xie
  • Patent number: 8883020
    Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Xunyuan Zhang, Xiuyu Cai
  • Patent number: 8883638
    Abstract: A method for manufacturing a damascene structure includes providing a substrate having a dielectric layer formed thereon, forming at least a trench in the dielectric layer, forming at least a via hole and a dummy via hole in the dielectric layer, forming a first conductive layer filling up the trench, the via hole and the dummy via hole on the substrate, and performing a chemical mechanical polishing process to form a damascene structure and simultaneously to remove the dummy via hole.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Chan-Yuan Hu, Ssu-I Fu
  • Patent number: 8883640
    Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Evan E. Patton, Theodore Cacouris, Eliot Broadbent, Steven T. Mayer
  • Patent number: 8883639
    Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 8878367
    Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: November 4, 2014
    Assignee: Xintec Inc.
    Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung
  • Patent number: 8859415
    Abstract: A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tajima, Akira Tojo
  • Patent number: 8853090
    Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8846436
    Abstract: An interlayer insulating film is disposed above an image pickup region and a peripheral region of the semiconductor substrate. An opening is formed in the interlayer insulating film at a position overlying a photoelectric conversion portion. A waveguide member is formed above the image pickup region and the peripheral region of the semiconductor substrate. A part of the waveguide member, which part is disposed above the peripheral region, is removed such that the interlayer insulating film is exposed.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: September 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kentaro Suzuki, Takehito Okabe, Hiroaki Sano, Junji Iwata
  • Patent number: 8841213
    Abstract: A method for manufacturing an interposer equipped with a plurality of through-hole electrodes comprises a laser light converging step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region in the object; an etching step of anisotropically etching the object after the laser light converging step so as to advance etching selectively along the modified region and form a plurality of through holes in the object, each through hole being tilted with respect to a thickness direction of the object and having a rectangular cross section; an insulating film forming step of forming an insulating film on an inner wall of each through hole after the etching step; and a through-hole electrode forming step of inserting a conductor into the through holes so as to form the through-hole electrodes after the insulating film forming step; wherein the plurality of through holes are arranged such that the through holes aligning in the tilted direction are staggered in a d
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 23, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8841212
    Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Thomas M. Shaw, Andrew H. Simon, Jean E. Wynne, Chih-Chao Yang
  • Patent number: 8835317
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin
  • Patent number: 8796852
    Abstract: A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: August 5, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 8778801
    Abstract: A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Bin Chiang, Hung-Chih Wang, Kuei-Pin Lee, Chi-Yu Chou, Yao Hsiang Liang
  • Patent number: 8766457
    Abstract: A bonding structure of a semiconductor package includes: a first conductive member configured to transmit an electrical signal; and a bonding pad configured to be electrically coupled to a surface of the first conductive member and comprising a plurality of sub bonding pads.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 1, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seong Cheol Kim
  • Patent number: 8735289
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Prechtl, Andreas Peter Meiser, Thomas Ostermann
  • Publication number: 20140131881
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng
  • Patent number: 8722527
    Abstract: The present invention discloses an integrated circuit (IC) comprising a bond pad (160); a substrate stack carrying a first layer (130) comprising conductive regions (135); and an interconnect layer (140) over the first layer (130) comprising a dielectric material portion (400) between the bond pad (160) and the substrate stack, said portion comprising a plurality of air-filled trenches (345) defining at least one pillar (340) of the dielectric material (400), at least said air-filled trenches (345) being capped by a porous capping layer (440). The interconnect layer (140), which typically is one of the uppermost interconnect layers of the IC, has an improved resilience to pressure exerted on the bond pad (160). The present invention further teaches a method for manufacturing such an IC.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: May 13, 2014
    Assignee: NXP B.V.
    Inventors: Didem Ernur, Romano Hoofman
  • Patent number: 8722539
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 13, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • Publication number: 20140124943
    Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, John E. Sheets, II
  • Publication number: 20140124947
    Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chita Chuang, Yao-Chun Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20140110838
    Abstract: Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Michael Rogalli, Wolfgang Lehnert
  • Publication number: 20140110855
    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng ZOU, Alex SEE, Huang LIU, Hai CONG
  • Patent number: 8703615
    Abstract: Disclosed are methods of depositing and annealing a copper seed layer. A copper seed layer may be deposited on a ruthenium layer disposed on a surface of a wafer and on features in the wafer. The thickness of the ruthenium layer may be about 40 Angstroms or less. The copper seed layer may be annealed in a reducing atmosphere having an oxygen concentration of about 2 parts per million or less. Annealing the copper seed layer in a low-oxygen atmosphere may improve the properties of the copper seed layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer, Huanfeng Zhu
  • Publication number: 20140103530
    Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Yen-Hao Shih
  • Publication number: 20140103520
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Publication number: 20140097538
    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin