Abstract: A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose the surface of the substrate; a protection film continuously covering the upper surface of the layered body except an electrode pad on the multilayer interconnection structure, and the sidewall and bottom surfaces of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.

Abstract: A laser processing method is provided, which, when cutting an object to be processed comprising a substrate and a multilayer part, formed on a front face of the substrate, including a functional device, can cut the multilayer part with a high precision in particular. In a state where a protective tape 22 is attached to the front face 16a of a multilayer part 16, a substrate 4 is irradiated with laser light L while using its rear face 4b as a laser light entrance surface, so as to form a modified region 7 within the substrate 4 along a line to cut, thereby generating a fracture 24 reaching the front face 4a of the substrate 4 from a front-side end part 7a of the modified region 7. Attaching an expandable tape to the rear face 4b of the substrate 4 and expanding it in the state where such a fracture 24 is generated can cut not only the substrate 4 but also the multilayer part 16 on the line to cut, i.e., interlayer insulating films 17a, 17b, with a favorable precision along the line to cut.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A wafer dividing method for dividing a wafer having a film on the front side thereof.

Abstract: Techniques for dicing wafer assemblies containing multiple metal device dies, such as vertical light-emitting diode (VLED), power device, laser diode, and vertical cavity surface emitting laser device dies, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, such techniques are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.

Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract: The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of integration, and a wiring board comprising the solder resist material and a semiconductor package. The solder resist material of the present invention can effectively suppress the warpage of a semiconductor package through a fiber base material-containing layer interposed between resin layers. The fiber base material-containing layer is preferably unevenly distributed in the thickness direction of the solder resist material.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system generates a laser beam, and a movement system relatively moves the semiconductor wafer with respect to the laser beam such that the semiconductor wafer is irradiated with a laser beam along the scribe lines to partially remove the multi-layered wiring structure from the semiconductor wafer along the scribe lines. An irradiation control system controls the irradiation of the semiconductor wafer with the laser beam along the scribe lines such that the alignment mark is left on the scribe line.

Abstract: A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail.

Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: When a single crystal semiconductor layer is bonded to a base substrate, a silicon oxide film is preferably used for one or both of the base substrate and a single crystal semiconductor substrate. According to this structure, an SOI layer having a strong bonding strength in a bonding portion can be obtained even when a substrate having an upper temperature limit of 700° C. or lower such as a glass substrate is used. In addition, a single crystal semiconductor substrate from which the single crystal semiconductor layer has been separated is reprocessed in such a manner that the single crystal semiconductor substrate is irradiated with laser light from the separation surface side of the single crystal semiconductor substrate, to melt the surface of the single crystal semiconductor substrate during the melting time per area of 0.5 microseconds to 1 millisecond. Then, the reprocessed single crystal semiconductor substrate is reused.

Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

Abstract: Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.

Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

Abstract: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface with a laser beam, wherein the treated area is ablated or melted by the beam and re-solidifies into a more planar profile, thereby reducing areas of stress concentration and stress risers that contribute to cracking and chipping during wafer singulation. Preferably, the treated area has a width less than that of a scribe street, but wider than the kerf created by a wafer dicing blade. Consequently, when the wafer is singulated, the dicing blade will preferably saw through treated areas only. It will be understood that the method of the preferred embodiments may be used to treat other areas of stress concentration and surface discontinuities on the wafer, as desired.

Abstract: A method of dividing a wafer having a plurality of areas defined by the plurality of streets formed in a lattice on the front surface, devices formed in the defined areas and an adhesive film for die bonding on the rear surface and put on a dicing tape affixed to an annular frame along the streets, the method comprising the steps of: forming a groove along the streets in the wafer by applying a first laser beam whose elliptic focal spot has a ratio of the long axis of the short axis of 15 to 20:1 along the streets formed on the wafer; and dividing the adhesive film along the grooves by applying a second laser beam whose elliptical focal spot has a ratio of the long axis to the short axis of 60 to 70:1 to the adhesive film through the grooves formed by the wafer dividing step.

Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.

Abstract: A method for forming a median crack and an apparatus for forming a median crack are provided, where the formation of a deep, straight median crack is possible, and an excellent broken surface of a brittle substrate can be gained as a result of breaking.

Abstract: A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.

Abstract: Disclosed herein is a method of dividing a wafer having a plurality of streets which are formed in a lattice pattern on the front surface and having devices which are formed in a plurality of areas sectioned by the plurality of streets into individual devices along the streets. The method includes applying a laser beam of a wavelength having permeability for the wafer along the streets to form a deteriorated layer along the streets in the inside of the wafer; forming a groove in areas corresponding to the streets from the rear side of the wafer; and exerting external force to the wafer where the deteriorated layer and the groove have been formed along the streets to divide the wafer into individual devices along the streets.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.

Abstract: A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.

Abstract: A semiconductor device includes a Si substrate, a gate insulating film formed on the Si substrate, the gate insulating film being formed of an oxide film containing at least one selected from the group of Zr, Hf, Ti and a lanthanoid series metal, and having a single local minimal value on a high binding energy side of an inflection point in first differentiation of an O1s photoelectron spectrum, and a gate electrode formed on the gate insulating film.

Abstract: A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

Abstract: In a wafer processing method for penetrating a wafer by use of a laser processing apparatus including a chuck table for holding the wafer, laser beam irradiation means for irradiating the wafer held on the chuck table with a laser beam, and imaging means for imaging the wafer held on the chuck table, the chuck table includes a chuck table main body, a holding member disposed on an upper surface of the chuck table main body and having a holding surface for holding an entire surface of the wafer, the holding member comprising a transparent or translucent member, and a light emitting body disposed laterally of a side of the holding member opposite to the holding surface.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: The invention concerns a method of collective bonding of individual chips on a strained substrate (44), which comprises the following steps: functionalised layers (40) are arranged on a support (41), in an adjacent non-contiguous manner, with a space e between two neighboring layers (40), a calibrated drop of adhesive (43) is deposited on each of these functionalised layers, the strained substrate (44) is transferred onto these drops of adhesive, the parts of the assembly thereby formed are singularized to produce chips (45) bonded to the surface of strained substrate. The invention also concerns a method of placing under strain a semiconductor reading circuit by a substrate in a material of different coefficient of expansion.

Abstract: A thin semiconductor film is crystallized in a high yield by being irradiated with laser light. An insulating film, a semiconductor film, an insulating film, and a semiconductor film are stacked in this order over a substrate. Laser light irradiation is performed from above the substrate to melt the semiconductor films of a lower layer and an upper layer, whereby the semiconductor film of the lower layer is crystallized. With the laser light irradiation, the semiconductor film of the upper layer changes to a liquid state, thereby reflecting the laser light and preventing the semiconductor film of the lower layer from being overheated with the laser light. Further, by melting the semiconductor film of the upper layer as well, time for melting the semiconductor film of the lower layer can be extended.

Abstract: A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed after said step of patterning the metallic electrode.

Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.

Abstract: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface, and having test metal patterns which are formed on the streets, comprising the steps of: a laser beam application step for carrying out laser processing to form a dividing start point along a street on both sides of the test metal patterns by applying a laser beam along the street on both sides of the test metal patterns in the street formed on the wafer; and a dividing step for dividing the wafer which has been laser processed to form dividing start points along the dividing start points by exerting external force to the wafer, resulting in leaving the streets having the test metal patterns formed thereon behind.

Abstract: A wafer laser processing method for forming grooves along streets by applying a pulse laser beam along the streets for sectioning a plurality of devices of a wafer having the plurality of devices which are composed of a laminate consisting of an insulating film and a functional film, on the front surface of a substrate, wherein the pulse laser beam is set to have a repetition frequency of 150 kHz to 100 MHz and an energy per unit length of 5 to 25 J/m.

Abstract: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Abstract: A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die. Additionally, the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.

Abstract: A rewiring substrate strip and a method of producing a rewiring substrate strip is disclosed. In one embodiment, the rewiring substrate strip has several semiconductor component positions for semiconductor components. The semiconductor component positions are arranged in rows and columns. In this arrangement, several semiconductor component positions are combined to form one component group. The semiconductor components of a component group are arranged with respect to one another in such a manner that an individual semiconductor component is rotated by 90° with respect to four adjacent semiconductor components.

Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

Abstract: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface and test metal patterns which are formed on the streets, having a metal pattern breaking step for forming a break line in the test metal patterns by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set near the test metal patterns; a deteriorated layer forming step for forming a deteriorated layer along the streets above the break lines in the inside of the wafer by applying a pulse laser beam having permeability to the wafer to the rear surface of the wafer with its focal point set to a position above the break lines in the inside of the wafer; and a dividing step.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A wafer laser processing method for forming a deteriorated layer along streets in the inside of a wafer having streets formed in a lattice pattern on the front surface, the method comprising: an undulation area deteriorated layer forming step for applying a laser beam along the streets to the undulating area of the wafer without activating the focal point position adjustment means to form a deteriorated layer along the streets in the inside of the undulating area of the wafer; and a stable holding area deteriorated layer forming step for applying a laser beam along the streets to a stable holding area other than the undulating area of the wafer while the focal point position adjustment means is controlled based on a detection signal from the height position detection means to form a deteriorated layer along the streets in the inside of the stable holding area of the wafer.