With Subsequent Division Of Substrate Into Plural Individual Devices (epo) Patents (Class 257/E21.599)

  • Patent number: 10211104
    Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 19, 2019
    Assignee: Disco Corporation
    Inventors: Yuta Yoshida, Hironari Ohkubo
  • Patent number: 10164144
    Abstract: Embodiments transfer thin layers of material utilized in electronic devices (e.g., GaN for optoelectronic devices), from a donor to a handle substrate. Certain embodiments employ bond-and-release system(s) where release occurs along a cleave plane formed by implantation of particles into the donor. Some embodiments may rely upon release by converting components from solid to liquid under carefully controlled thermal conditions (e.g., solder-based materials and/or thermal decomposition of Indium-containing materials). Some embodiments utilize laser-induced film release processes using epitaxially grown or implanted regions as an optically absorptive region. A single bond-and-release sequence may involve processing an exposed N-face of GaN material. Multiple bond-and-release sequences (involving processing an exposed Ga-face of GaN material) may be employed in series, for example utilizing a temporary handle substrate as an intermediary.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 25, 2018
    Assignee: QMAT, Inc.
    Inventors: Francois J. Henley, Sien Kang, Mingyu Zhong, Minghang Li
  • Patent number: 10163713
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 25, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 10157765
    Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
  • Patent number: 10131147
    Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, first discontinuous slotted recesses in a first surface of a wafer. The first discontinuous slotted recesses may be arranged in parallel, spaced apart relation. The method may further include forming, by sawing with the rotary saw blade, second discontinuous slotted recesses in a second surface of the wafer aligned and coupled in communication with the first continuous slotted recesses to define through-wafer channels. In another embodiment, the first and second plurality of discontinuous recesses may be formed by respective first and second rotary saw blades.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Kenneth J. Stewart
  • Patent number: 10115857
    Abstract: A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 30, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Hiroki Okamoto, Hiroaki Tamemoto, Junya Narita
  • Patent number: 10096742
    Abstract: A light emitting device having improved light extraction is provided. The light emitting device can be formed by epitaxially growing a light emitting structure on a surface of a substrate. The substrate can be scribed to form a set of angled side surfaces on the substrate. For each angled side surface in the set of angled side surfaces, a surface tangent vector to at least a portion of each angled side surface in the set of angled side surfaces forms an angle between approximately ten and approximately eighty degrees with a negative of a normal vector of the surface of the substrate. The substrate can be cleaned to clean debris from the angled side surfaces.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 9, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jianyu Deng, Alexander Dobrinsky, Xuhong Hu, Remigijus Gaska, Michael Shur
  • Patent number: 10096556
    Abstract: A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair of two sides extending in a first direction and a pair of two sides extending in a second direction. The conductive layer is provided on the substrate and extending along a periphery of the substrate. The conductive layer extends and zigzags toward the first direction.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Kumai
  • Patent number: 10090254
    Abstract: A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound covers a center region of the wafer, and leaves an edge ring of the wafer not covered. An opening is formed to extend from the front surface of the wafer into the wafer, wherein the opening is in the edge ring of the wafer. A backside grinding is performed on the wafer until the opening is revealed through a back surface of the wafer. The method further includes determining a position of a scribe line of the wafer using the opening as an alignment mark, and sawing the wafer from a backside of the wafer by sawing through the scribe line.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10090198
    Abstract: Disclosed is a method for separating a substrate (1) along a separation pattern (4), in which method a substrate (1) is provided and an auxiliary layer (3) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate along the separation pattern in the form of an impurity. The substrate is broken along the separation pattern. A semiconductor chip (15) is also disclosed.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 2, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Mathias Kaempf
  • Patent number: 10050013
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Patent number: 10043701
    Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 7, 2018
    Assignee: Infineon Technologies AG
    Inventors: Adolf Koller, Franco Mariani, Katharina Umminger
  • Patent number: 10043761
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
  • Patent number: 9966297
    Abstract: According to the present invention, there is provided a semiconductor wafer protective film including a substrate layer (A) and an adhesive layer (C) formed on the substrate layer (A), in which the substrate layer (A) includes polymer, and a solubility parameter of the polymer determined by a Van Krevelen method is equal to or greater than 9.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 8, 2018
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Akimitsu Morimoto, Makoto Kataoka, Hideki Fukumoto
  • Patent number: 9917008
    Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 13, 2018
    Assignee: GULA CONSULTING LIMITED LIABILITY COMPANY
    Inventor: Ernest E. Hollis
  • Patent number: 9893230
    Abstract: A method for producing a lighting module is provided. The method includes providing a light source substrate populated with at least one semiconductor light source, laterally surrounding the at least one semiconductor light source by a wall, applying at least one prefabricated diffuser element to at least one semiconductor light source, introducing potting compound into the space surrounded by the wall up to a height at which both the at least one semiconductor light source, and potting at least part of the at least one diffuser element.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 13, 2018
    Assignee: OSRAM GmbH
    Inventor: Martin Reiss
  • Patent number: 9881828
    Abstract: Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a base tape, a DAF, and an adhesive layer for uniting the base tape and the DAF, imaging the wafer through the dicing tape to obtain an image of the wafer, detecting the positions of poor adhesion of the DAF from the image, storing the positions of poor adhesion detected above, dividing the wafer and the DAF into individual chips each having the DAF, curing the adhesive layer of the dicing tape by the application of ultraviolet light, selectively separating the chips with the DAF well adhered, at the boundary between the adhesive layer and the DAF according to the positions of poor adhesion stored above, and then picking up the chips with the DAF well adhered.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 30, 2018
    Assignee: DISCO CORPORATION
    Inventors: Shinji Yoshida, Yusaku Ito, Hirohide Yano
  • Patent number: 9881827
    Abstract: An embodiment includes a substrate treating apparatus comprising: a tape supply member configured to supply a tape to be attached to a substrate; a tape collection member configured to collect a surplus tape that remains after the tape is attached to the substrate; a support member disposed between the tape supply member and the tape collection member and configured to support the substrate while the tape is attached to the substrate; and a temperature adjustment member configured to adjust a temperature of the tape that is supplied from the tape supply member to the support member.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geunwoo Kim, Seunghee Lee, Hyun Kim, Ohchul Kwon, Sangho An, Seonju Oh, Yun-Sik Yoo
  • Patent number: 9859458
    Abstract: Embodiments transfer thin layers of material utilized in electronic devices (e.g., GaN for optoelectronic devices), from a donor to a handle substrate. Certain embodiments employ bond-and-release system(s) where release occurs along a cleave plane formed by implantation of particles into the donor. Some embodiments may rely upon release by converting components from solid to liquid under carefully controlled thermal conditions (e.g., solder-based materials and/or thermal decomposition of Indium-containing materials). Some embodiments utilize laser-induced film release processes using epitaxially grown or implanted regions as an optically absorptive region. A single bond-and-release sequence may involve processing an exposed N-face of GaN material. Multiple bond-and-release sequences (involving processing an exposed Ga-face of GaN material) may be employed in series, for example utilizing a temporary handle substrate as an intermediary.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 2, 2018
    Assignee: QMAT, INC.
    Inventors: Francois J. Henley, Sien Kang, Mingyu Zhong, Minghang Li
  • Patent number: 9842742
    Abstract: A method for thinning samples including the steps of: a) providing at least one sample having a front and a rear face, b) providing a frame substrate having a first face and a second face opposite the first, including a through-opening which opens into the first and second face, which is configured to receive the sample, c) positioning the sample so it is disposed in the through-opening, the front face being oriented to the same side as the first face, and d) thinning the frame substrate and the sample simultaneously from the first face and the front face, respectively, so that at the end of thinning, the faces extend substantially in the same plane, the thinning being carried out using a grinder, the frame substrate and the sample being disposed on a rotary disk held in place by aspiration, the flanks of the sample remaining free during the thinning.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 12, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jérôme Dechamp, Hubert Moriceau, Marc Zussy
  • Patent number: 9824827
    Abstract: The instant disclosure relates to a method for making solid electrolytic capacitor package structure with improved conductive terminals. The first step is to provide at least one conductive terminal having an electrical contact portion and a lead-out portion. The next step is to remove a portion of mantle layer from the surface of the core layer of at least one conductive terminal by a dry-type process. The next step is to sequentially stack together a plurality of stacked-type capacitors to form a capacitor unit and then electrically connect the capacitor unit to at least one conductive terminal. The next step is to form a package body to encapsulate the capacitor unit and the electrical contact portion of at least one conductive terminal. The last step is to bend the lead-out portion of at least one conductive terminal to an axis that extends along the surface of the package body.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: November 21, 2017
    Assignee: APAQ TECHNOLOGY CO., LTD.
    Inventors: Chi-Hao Chiu, Ming-Tsung Chen, Kun-Huang Chang
  • Patent number: 9773745
    Abstract: A semiconductor device includes a substrate layer, a redistribution layer (RDL) disposed over the substrate layer, a conductive bump disposed over the RDL, and a molding disposed over the RDL and surrounding the conductive bump, wherein the molding includes a protruded portion laterally protruded from a sidewall of the substrate layer and away from the conductive bump.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 9742147
    Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9711473
    Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 18, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chin-Cheng Kuo, Ying-Te Ou, Lu-Ming Lai
  • Patent number: 9653644
    Abstract: A method for manufacturing a semiconductor element includes providing a wafer having a sapphire substrate and a semiconductor stacked body disposed on the sapphire substrate, performing a first scanning of a portion of the sapphire substrate in which a laser beam is irradiated into an interior of the sapphire substrate, performing a second scanning of the portion of the sapphire substrate in which a laser beam is irradiated into the interior of the sapphire substrate, the second scanning occurring after the first scanning and before a void is produced in the interior of the sapphire substrate irradiated with the laser beam in the first scanning, and separating the wafer into a plurality of semiconductor elements.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 16, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Hiroaki Tamemoto, Ryota Taoka
  • Patent number: 9646744
    Abstract: A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 9, 2017
    Assignee: LITTELFUSE, INC.
    Inventors: Mario G. Sepulveda, Martin G. Pineda, Anthony Vranicar, Kedar V. Bhatawadekar, Minh V. Ngo, Dov Nitzan
  • Patent number: 9633902
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes: selectively forming a plurality of mask layers on a first surface of a semiconductor substrate, and the semiconductor substrate having the first surface and a second surface; dividing the semiconductor substrate by forming a gap piercing from the first surface to the second surface of the semiconductor substrate, the gap being formed by dry-etching the first surface of the semiconductor substrate exposed between the plurality of mask layers, and a width of the gap on the second surface side being larger than a width of the gap on the first surface side; and forming a first electrode under a reduced-pressure atmosphere on the first surface of the semiconductor substrate after the semiconductor substrate being divided.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Matsui, Mie Matsuo, Chiaki Takubo
  • Patent number: 9613913
    Abstract: Provided are a method of forming an electromagnetic interference (EMI) shielding layer of a ball grid array (BGA) semiconductor package, and a base tape used in the method, and more particularly, a method of forming a shielding layer for blocking EMI, on an upper surface and lateral surfaces of a BGA semiconductor package having a lower surface, on which a plurality of solder balls are formed, and a base tape used in the method. According to the method of forming an EMI shielding layer of a BGA semiconductor package, the EMI shielding layer may be formed on the BGA semiconductor package quickly, easily, and effectively by using the base tape, thereby not only improving process productivity but also remarkably reducing the manufacturing costs.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 4, 2017
    Assignee: PROTEC CO., LTD.
    Inventors: Sung Hwan Choi, Tae Sup Han
  • Patent number: 9586331
    Abstract: A dividing method for a disk-shaped workpiece having a plurality of first division lines and a plurality of second division lines intersecting the first division lines. The workpiece is cut along the first and second division lines by using a cutting blade in a down cut manner as supplying a cutting fluid to the cutting blade, wherein the workpiece is fully cut in a thickness direction thereof to obtain a plurality of chips. The dividing method includes a first cutting step of cutting the workpiece along the first division lines and a second cutting step of cutting the workpiece along the second division lines. In at least the second cutting step, the outer circumference of the workpiece at the cut end of each second division line is not cut to form an uncut region, thereby suppressing the formation of waste chips.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: March 7, 2017
    Assignee: Disco Corporation
    Inventor: Shunichiro Hirosawa
  • Patent number: 9570314
    Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: February 14, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: William John Nelson, Nathapong Suthiwongsunthorn, Beng Yeung Ho, Poh Leng Wilson Ong
  • Patent number: 9564524
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Patent number: 9530930
    Abstract: Vertical high power LEDs are the technological choice for the application of general lighting due to their advantages of high efficiency and capability of handling high power. However, the technologies of vertical LED fabrication reported so far involve the wafer-level metal substrate substitution which may cause large stress due to the mismatch between metal substrate and LED layer. Moreover, the metal substrate has to be diced to separate LED dies which may cause metal contamination and thus increase the leakage current. These factors will lower the yield of LED production and increase the cost as well. The present invention is to disclose a novel method for the fabrication of GaN vertical high power LEDs and/or a novel method for the fabrication of GaN vertical high power LEDs which is compatible to mass production conditions. The novelty of the invention is that the island metal plating is conducted with the help of pattern formation techniques.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 27, 2016
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Wei Liu, Zi-Hui Zhang, Zhengang Ju, Xueliang Zhang, Yun Ji, Swee Tiam Tan, Xiao Wei Sun, Hilmi Volkan Demir
  • Patent number: 9490155
    Abstract: A wafer processing method including a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer along each division line to thereby form a modified layer inside the wafer along each division line, and a back grinding step of grinding the back side of the wafer to reduce the thickness of the wafer to a predetermined thickness and also divide the wafer along each division line where the modified layer is formed as a break start point, thereby obtaining individual device chips. Prior to performing the back grinding step, the method further includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, the protective tape having an adhesive layer curable by the application of ultraviolet light, and an adhesive layer curing step of applying ultraviolet light to the protective tape to thereby cure the adhesive layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 8, 2016
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 9490138
    Abstract: Methods are provided for processing a substrate in single substrate tool. In one embodiment, the method includes providing the substrate in the single substrate tool, applying a first processing fluid at a first temperature greater than 100° C. to a lower surface of the substrate to heat the substrate to approximately the first temperature, and applying a second processing fluid at a second temperature greater than 100° C. to an upper surface of the substrate.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: November 8, 2016
    Assignee: TEL FSI, INC.
    Inventor: Kevin L. Siefering
  • Patent number: 9455173
    Abstract: A semiconductor piece manufacturing method includes: a process of forming a fine groove on a front surface side including a first groove portion having a width that is gradually narrowed from a front surface of a semiconductor substrate W toward a rear surface thereof; a process of attaching a dicing tape having an adhesive layer on the front surface after the fine groove on the front surface side is formed; a process of forming a groove on a rear surface side having a width greater than the width of the fine groove on the front surface side along the fine groove on the front surface side from a rear surface side of the substrate by a rotating dicing blade; and a process of separating the dicing tape from the front surface after the groove on the rear surface side is formed.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: September 27, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Mutsuya Takahashi, Shuichi Yamada, Michiaki Murata
  • Patent number: 9450381
    Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9373609
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Meng Tong Ong, Thiam Huat Lim, Kok Chai Goh
  • Patent number: 9362174
    Abstract: A device wafer processing method includes, a groove forming step in which grooves with a predetermined depth are formed in the front side of a device wafer; a plate attaching step in which a plate is attached to the front side of the wafer through an adhesive; a grinding step in which the wafer is held by a holding table through the plate so as to expose the back side of the wafer, and the back side is ground to expose the grooves at the back side of the wafer, thereby dividing the wafer to form a plurality of chips. The method further includes: a film attaching step in which a film is attached to the back side of the wafer; and a dicing step in which the film is diced along division lines from the side of the back side of the wafer.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 7, 2016
    Assignee: Disco Corporation
    Inventor: Yasutaka Mizomoto
  • Patent number: 9293372
    Abstract: A wafer has a substrate, a functional layer and division lines. The wafer is held on a chuck table with a protective member attached to the front side of the functional layer in contact with the chuck table. The height of the back side of the wafer is detected in a Z direction along each division line while moving the chuck table in an X direction. An X coordinate is recorded for each division line, as well as a corresponding Z coordinate. A cutting blade is positioned on the back side of the wafer and moved in the Z direction according to the recorded X and Z coordinates while moving the chuck table in the X direction to thereby form a cut groove having a depth not reaching the functional layer, with a part of the substrate left between the bottom of the cut groove and the functional layer.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 22, 2016
    Assignee: Disco Corporation
    Inventors: Kensuke Nagaoka, Yuki Ogawa, Tsubasa Obata, Yuri Ban
  • Patent number: 9190309
    Abstract: In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release substrate from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased and the wafer processing tape can be suppressed from being peeled off from the wafer ring during processes.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: November 17, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
  • Patent number: 9041162
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Patent number: 9040389
    Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
  • Patent number: 9029200
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Patent number: 9029199
    Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Shinichi Sakurada
  • Patent number: 9023717
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing a semiconductor device according to one embodiment includes a step of cutting, in a dicing region arranged between two chip regions adjacent to each other, a wafer along an extending direction of the dicing region. The dicing region has therein a plurality of metal patterns in a plurality of columns. In the step of cutting the wafer, one or more of the columns of metal patterns formed in a plurality of columns are removed, and the metal patterns of the column(s) different from the above-mentioned one or more of the columns are not removed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Nakagawa, Shunichi Abe
  • Patent number: 9012305
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with an anisotropic plasma process non-reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Jungrae Park, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9012992
    Abstract: A transfer layer includes a transparent substrate. A buffer layer is formed on the transparent substrate that comprises PbO, GaN, PbTiO3, La0.5Sr0.5CoO3 (LSCO), or LaxPb1-xCoO3 (LPCO) so that separation between the buffer layer and the transparent substrate occurs at substantially high temperatures.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Il-Doo Kim, Harry L. Tuller, Yong Woo Choi, Akintunde I. Akinwande
  • Patent number: 9006040
    Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chang Hsieh, Kong-Beng Thei
  • Patent number: 8993413
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte