Abstract: Foreign matter formed over (or adhered to) a surface of a lead is reliably removed. A laser beam is applied to a residual resin (sealing body) which is formed in (or adhered to) a region surrounded by a sealing body (a first sealing body), a lead exposed (projected) from the sealing body, and a dam bar. The foreign matter formed over (or adhered to) the surface of the lead can be reliably removed by washing the surface of the lead after the removal of the residual resin. Thus, in a subsequent plating step, the reliability (wettability, adhesion with the lead) of a plating film to be formed over the surface of the lead can be improved.

Abstract: A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A through portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meet. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode.

Abstract: A package includes a substrate provided with a passing opening and a MEMS device. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated sensitive to the chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the passing opening. A protective package incorporates the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device exposed through the passing opening of the substrate.

Abstract: An apparatus and method of improving power noise of a Ball Grid Array (BGA) package are provided. The method includes securing a space for a passive element mounting pad, on which a passive element can be mounted, adjacent to a power pad on a Printed Circuit Board (PCB) corresponding to a power pin of the BGA package, mounting the passive element on the passive element mounting pad, and mounting the BGA package at a position on the PCB, wherein the position on the PCB overlaps the passive element and further wherein the BGA package is mounted above the passive element.

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Abstract: In a wiring substrate according to the present invention, a base wiring board is constructed by stacking a plurality of unit wiring boards each having wiring patterns which enable an electrical connection between upper and lower sides, in a state that the plurality of unit wiring boards are connected to each other via a connection terminal, and a silicon interposer is stacked on the base wiring board via a connection terminal, and a resin portion is filled in a gap between the plurality of unit wiring boards as well as a gap between the base wiring board and the silicon interposer, and a resin portion serves as a substrate which integrates the base wiring board and the silicon interposer.

Abstract: The present invention relates to a method for manufacturing thin-film photovoltaic panels by the use of a sealing means composed by a polymeric tie layer comprising getter system composed of a polymer with low H2O transmission having dispersed in its inside H2O sorption material, and two outer polymeric layers with the composite getter system therebetween, as well as to polymeric tri-layer for the manufacturing of photovoltaic panels.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.

Abstract: A MEMS component includes a substrate in which at least one cavity is present. The cavity is closed off toward an active side of the substrate. An inactive side is arranged opposite the active side of the substrate, and the substrate is covered with a covering film on the inactive side.

Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.

Abstract: A method of manufacturing a semiconductor device including (1) providing a metal plate having an upper surface and a back surface, the metal plate including a plurality of lids disposed in matrix, which are defined by a first groove formed from the upper surface, (2) providing a ceramic sheet having an upper surface and a back surface, the ceramic sheet including a plurality of headers disposed in matrix, which are defined by a second groove formed from the back surface, (3) fixing the metal plate on the ceramic sheet by facing the back surface of the metal plate to the upper surface of the ceramic sheet, wherein the first groove is aligned with the second groove, and (4) dividing the metal plate and the ceramic sheet along the first and the second grooves.

Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

Abstract: A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.

Abstract: A semiconductor module and a method for producing the same is disclosed. In one embodiment, the semiconductor module has adjacent regions on a common wiring substrate in a common plastic housing composition. The regions are thermally decoupled by a thermal barrier. Semiconductor chips whose evolution of heat loss differs are arranged in these thermally separate regions, the thermal barrier ensuring that the function of the more thermally sensitive semiconductor chip is not impaired by the heat-loss-generating semiconductor chip.

Abstract: Hermetically sealed packages having organic electronic devices are presented. A number of sealing mechanisms are provided to hermetically seal the package to protect the organic electronic device from environmental elements. A metal alloy sealant layer is employed proximate to the organic electronic device. Alternatively, a metal alloy sealant layer in combination with primer layer may also be implemented. Further, superstrates and edge wraps may be provided to completely surround the organic electronic device.

Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.

Abstract: Various semiconductor chip carrier substrate circuit tuning apparatus and methods are disclosed. In one aspect, a method of manufacturing is provided that includes assembling a semiconductor chip carrier substrate with a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is placed in the semiconductor chip carrier substrate. The inductor is electrically connected between the first and second input/output sites. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site due to coupling to a second conductor in the semiconductor chip carrier substrate.

Abstract: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.

Abstract: The present invention relates to a wafer level package and a method of manufacturing the same. The wafer level package includes a first substrate including a first region and second regions with grooves around the first region; a semiconductor device positioned in the first region; first sealing members positioned in the grooves; a second substrate including projection units corresponding to the second regions in order to form a cavity corresponding to the first region; and second sealing members which are positioned above the projection units and laminate the first and second substrates to each other by being bonded to the first sealing members, and can prevent the sealing members from flowing to any region except for the sealing regions.

Abstract: A protective thin film coating for device packaging. A dielectric thin film coating is formed over die and package substrate surfaces prior to applying a molding compound. The protective thin film coating may reduce moisture penetration from the bulk molding compound or the interface between the molding compound and the die or substrate surfaces.

Abstract: The present invention relates to a light-emitting device comprising at least one light-emitting diode, which emits light, and a housing arranged to receive at least a portion of said light. The housing comprises a translucent inorganic material and is provided with at least one recess, which comprises positioning and orientating means. The at least one light-emitting diode is arranged in the at least one recess and is positioned and orientated by said positioning and orientating means, and a translucent inorganic contact layer material is arranged between the at least one light-emitting diode and the housing in the at least one recess to receive at least portion of the light and to connect said light-emitting diode to said housing.

Abstract: The invention relates to MEMS devices. In one embodiment, a micro-electromechanical system (MEMS) device comprises a resonator element comprising a semiconducting material, and at least one trench formed in the resonator element and filled with a material comprising oxide. Further embodiments comprise additional devices, systems and methods.

Abstract: A method for fabricating a printed circuit board having semiconductor components embedded therein is provided. A carrier board having at least a predetermined hole area is provided. A plurality of through holes are formed in the surround of the predetermined hole area on the carrier board. A rectangular cavity is formed by punching to remove the predetermined hole area, and a plurality of through holes are formed around the rectangular cavity The through holes facilitate receipt of the semiconductor chip and filling of a fixing material in the rectangular cavity, to avoid displacement of the semiconductor chip in subsequent fabricating steps that would otherwise cause a drawback, that is, a wiring to be formed later is improperly electrically connected to the semiconductor chip.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: A semiconductor module and a method. One embodiment provides a housing with a housing frame and a pluggable carrier which is plugged in the housing frame. The pluggable carrier is equipped with a lead which includes an internal portion which is arranged inside the housing, and an external portion which is arranged outside the housing. The internal portion is electrically coupled to an electric component of the power semiconductor module. The external portion allows for electrically coupling the power semiconductor module.

Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.

Abstract: A method for assembling an electronic component on a printed circuit board includes following steps. Firstly, a printed circuit board substrate including a central main portion and a peripheral unwanted portion is provided. Secondly, electrically conductive patterns and reinforcing patterns are formed on the main portion and the unwanted portion respectively. Thirdly, an electronic component is mounted on the main portion and electrically connected with the electrically conductive patterns. Fifthly, the unwanted portion is removed.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: A semiconductor component includes a semiconductor chip provided with a passivation layer that covers the topmost interconnect structure of the semiconductor chip whilst leaving contact areas free. The passivation layer is in direct adhesive contact with the plastic housing composition of the semiconductor component. The passivation layer includes a polymer with embedded mineral-ceramic nanoparticles.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.

Abstract: A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.

Abstract: Apparatus and methods are provided for packaging IC (integrated circuit) chips to enable both optical access to the back side of an IC chip and electrical access to the front side of the IC chip.

Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Abstract: A semiconductor device comprises a package having a cavity in the interior thereof, a chip having a semiconductor element, a board having the chip fixed to a first region on the upper face thereof, and an adhesive portion formed in a second region on the bottom face of the board in order to fix the board to a first face of the cavity, the second region being a region on the board other than the region thereof underneath the first region.

Abstract: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic light-emitting transistor, a composite layer containing an organic compound having a hole-transporting property and a metal oxide is used as part of the electrode that injects holes among source and drain electrodes, and a composite layer containing an organic compound having an electron-transporting property and an alkaline metal or an alkaline earth metal is used as part of the electrode that injects electrons, where either composite layer has a structure of being in contact with an organic semiconductor layer.

Abstract: A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the semiconductor device and the contactor board are in physical contact. A continuous electrically conductive path is formed with electrically conductive elements involving both the semiconductor device and the contactor board. A complete electrical circuit involving both the semiconductor device and the contactor board is formed only when the relative orientation of the semiconductor device and the contactor board have predetermined relationship and the electrically conductive elements of the two boards are in good physical contact.

Abstract: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A power module package including a fully enclosed package comprising sidewalls; wherein at least one of said sidewalls includes a conductive substrate; wherein circuit elements are mounted on said conductive substrate on a first side comprising an inner side of said enclosed package; and, wherein a majority area of a second side of said conductive substrate is exposed, the power package has an improved interconnection configuration and compact power I/O terminals, offering low electrical parasitics, a plurality of individual power module packages can be attached seamlessly and positioned in a liquid coolant with multiple top portion open channels, as well as attached to a laminar power connector (busbar) to form various electrical power conversion topologies, the module offers low thermal resistance and low electrical parasitics, in addition to small volume, light weight and high reliability.

Abstract: A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Abstract: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.

Abstract: A method and system is disclosed for facilitating miniaturization of an electronic device by efficiently utilizing available space. Specifically, in an exemplary embodiment, there is provided an electronic device comprising a substrate, a cavity formed in the substrate, and a bridge coupled to the substrate such that it spans the cavity. Further, the device may include a semiconductor device coupled to the bridge such that the semiconductor device is positioned within the cavity. In some embodiments, the bridge may include a tape automated bonding (TAB) tape having various layers, including a layer configured to provide electromagnetic shielding.

Abstract: A semiconductor sensor includes an adhesive film for suppressing thermal stress transfer to a semiconductor sensor chip. More specifically, the adhesive film includes a first layer and a second layer. An elasticity modulus of the first layer is lower than that of the second layer, and the second layer has a water absorption smaller than that of the first layer. One surface of a semiconductor wafer is in contact with the first layer. Once the semiconductor wafer and the adhesive film are diced into a plurality of sensor chips, the sensor chip with the adhesive film is mounted on a sensor package via the second layer interposed therebetween.

Abstract: Apparatus, methods, and systems for bonding a cover wafer to a MEMS threshold sensors located on a silicon disc. The cover wafer is trenched to form a region when bonded to the silicon wafer that produces a gap over the contact bond pads of the MEMS threshold sensor. The method includes a series of cuts that remove part of the cover wafer over the trenches to permit additional cuts that may avoid the contact bond pads of the MEMS threshold sensor. In addition the glass frit provides for isolation of the sensor with a hermetic seal. The cavity between the MEMS threshold sensor and the cover wafer may be injected with a gas such as nitrogen to influence the properties of the MEMS threshold sensor. The MEMS threshold sensor may be utilized to sense a threshold for pressure, temperature or acceleration.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic light-emitting transistor, a composite layer containing an organic compound having a hole-transporting property and a metal oxide is used as part of the electrode that injects holes among source and drain electrodes, and a composite layer containing an organic compound having an electron-transporting property and an alkaline metal or an alkaline earth metal is used as part of the electrode that injects electrons, where either composite layer has a structure of being in contact with an organic semiconductor layer.