Abstract: A three dimensional multilayer circuit (400) includes a via array (325, 330) made up of a set of first vias (325) and a set of second vias (330) and an area distributed CMOS layer (310) configured to selectively address said first vias (325) and said second vias (330). At least two crossbar arrays (305, 420) overlay the area distributed CMOS layer (310). These crossbar arrays (305, 420) include a plurality of intersecting crossbar segments (320, 322) and programmable cross-point devices (315) which are interposed between the intersecting crossbar segments (320, 322). The vias (325, 330) are connected to the crossbar segments (320, 322) such that each programmable crosspoint devices (315) can be uniquely accessed using a first via (325) and a second via (330).

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: A non-volatile sampler including a row line for receiving an input signal to be sampled, the row line intersecting a number of column lines, non-volatile storage elements being disposed at intersections between the row line and the column lines; a bias voltage source connected to the column lines, the bias voltage source for selectively applying a bias voltage to at least one of the non-volatile storage elements to cause the at least one of the storage elements to store a sample of the input signal at the instance the bias voltage is applied.

Abstract: Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed.

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Abstract: A method for manufacturing a semiconductor device package to provide RF shielding. The device is mounted on a laminated substrate having conducting pads on its top surface. A molding compound covers the substrate top surface and encapsulates the devices. The substrate is disposed on a tape; the molding compound and the substrate are cut through, forming package units separated by the saw cut width and exposing a portion of a conducting pad. In an embodiment, the tape is stretched to widen the gap between package units. A conductive shield is applied to cover each package unit and to make electrical contact with the exposed conducting pad portion, thereby connecting to a ground trace beneath the device and providing RF shielding for the device. A single-unit molding process may be used, in which the conducting pad is exposed during and after molding.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F2 and comprises a plurality of conductors fabricated as doped semiconductor conducting lines in the substrate such that, during normal operation, an unselected conductor has a zero bias to the substrate and a selected conductor has a reverse bias to the substrate for minimizing current leakage

Abstract: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive.

Abstract: A method is described for reducing dielectric overetch. The method includes: (1) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; (2) depositing second dielectric fill directly on the planar surface; and (3) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.

Abstract: A phase-change oscillator and pulse generator, and related methods, are provided. The phase-change oscillator and pulse generator can include a capacitor, a switching element coupled in parallel connection with the capacitor, and a resistor coupled in series with the switching element and configured to supply a bias voltage to the switching element. The switching element can have a low-resistance state in a liquid-phase and a high-resistance state in a solid phase. In addition, the switching element can have a negative thermal coefficient of resistance. In an aspect, the switching element comprises a wire of a semiconducting material having negative thermal coefficient of resistance, such semiconducting material can be doped n-type or p-type. In an aspect, the liquid-phase is a molten state of the wire and the solid-phase is a solid state of the wire. An oscillatory signal is based at least on transitioning between the molten state and the solid state.

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.

Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract: A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.

Abstract: A method for assembling a microelectronic device is provided comprising the step of adhering a die to a substrate using a convex die attachment process. The convex die attachment process generally comprises a) providing a die having an underfill material thereon, b) picking up and inverting the die, c) heating the underfill until it liquefies at least slightly and forms a convex surface, and d) placing the die on a substrate.

Abstract: Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.

Abstract: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin.

Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

Abstract: The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts.

Abstract: An integrated circuit having an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. At least an (i?1)-th level of conductors of the L-PSN comprising Li?1 number of conductors selectively couple to the i-th level of conductors comprising Ii number of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((Ii?1×D[i])+Ii) number of switches where each conductor of the Li?1 number of conductors selectively couples to at least (D[i]+1) number of conductors of the Ii number of conductors, at least one conductor from each of the D[i] sets of conductors, for D[i] greater than one. The integrated circuit can be used in various electronic devices.

Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract: One embodiment is a method of forming a circuit structure. The method comprises forming a first amorphous layer over a substrate; forming a first glue layer over and adjoining the first amorphous layer; forming a second amorphous layer over and adjoining the first glue layer; and forming a plurality of posts separated from each other by removing a first portion of the first amorphous layer and a first portion of the second amorphous layer. At least some of the plurality of posts each comprises a second portion of the first amorphous layer, a first portion of the first glue layer, and a second portion of the second amorphous layer.

Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

Abstract: An upper module board on which an integrated chip component with a low upper temperature limit is mounted and a lower module board on which a heat-generating semiconductor chip, a single chip component and an integrated chip component are mounted are electrically and mechanically connected via a plurality of conductive connecting members, and these are sealed together with mold resin. In such a circumstance, a shield layer made up of a stacked film of a Cu plating film and a Ni plating film is formed on side surfaces of the upper and lower module boards and surfaces (upper and side surfaces) of the mold resin, thereby realizing the electromagnetic wave shield structure.

Abstract: A display device capable of implementing the light shielding effect and process simplification, and a method of manufacturing the display device. The display device includes a transistor formed in a first region on a substrate, a pixel electrode formed in a second region on the substrate, a buffer layer formed beneath the transistor in the first region, and a light shielding layer formed between the buffer layer and the substrate in the first region. In the display device, the light shielding layer may include a semiconductor material.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: A programmable crosspoint device with an integral diode includes a first crossbar, a second crossbar, a metallic interlayer, and a switching oxide layer interposed between the first crossbar and the metallic interlayer. The switching oxide layer has a low resistance state and high resistance state. The programmable crosspoint device also includes an integral diode which is interposed between the second crossbar layer and the metallic interlayer, the integral diode being configured to limit the flow of leakage current through the programmable crosspoint device in one direction. A method for forming a programmable crosspoint device with an integrated diode is also provided.

Abstract: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.

Abstract: A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. A bridging element electrically connects the first microelectronic element and the second microelectronic element. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

Abstract: An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.

Abstract: A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

Abstract: A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections.

Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.

Abstract: An integrated circuit chip is defined by a stack of several interconnected layers. The integrated circuit chip includes at least two layers of dissimilar metal patterned to define an array of integrated bimetallic thermocouples.

Abstract: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.