Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

Abstract: A process for fabricating a pendulous accelerometer, including the steps of: providing a first substrate having a top planar surface, etching a portion of the first substrate to a first predetermined depth from the top planar surface to form a plurality of first protrusions, providing a second substrate, etching a portion of the second substrate to a second predetermined depth to form a plurality of second protrusions, bonding planar surfaces of the first protrusions to planar surfaces of the second protrusions, and etching a portion of the first substrate from an opposite side of the first substrate to a third predetermined depth equal to or greater than the difference between the total thickness of the first substrate and the first predetermined depth to form a freely rotatable sensing plate that includes a substantially hollow proof mass.

Abstract: Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the portions of the support structures underlying the movable layer include a convex sidewall. In further embodiments, a portion of the support structure extends through an aperture in the movable layer and over at least a portion of the movable layer.

Abstract: A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer are sequentially formed over the substrate. A floating gate is defined in the memory cell region and the top layer and the first conductive layer of the high voltage circuit region are removed. The exposed silicon oxide layer is thickened. Thereafter, the top layer is removed and then a barrier layer is formed on the exposed surface of the floating gate. A second conductor layer is formed over the substrate, and then a gate is defined in the high voltage circuit region and a control gate is defined in the memory cell region.

Abstract: Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

Abstract: A MEMS apparatus has a MEMS device sandwiched between a base and a circuit chip. The movable member of the MEMS device is attached at the side up against the circuit chip. The movable member may be mounted on a substrate of the MEMS device or formed directly on a passivation layer on the circuit chip. The circuit chip provides control signals to the MEMS device through wire bonds, vias through the MEMS device or a conductive path such as solder balls external to the MEMS device.

Abstract: Provided is a substrate preparation method for a micro-electromechanical system (MEMS) fabrication process. The method includes the step of depositing at least four metal layers interspersed with interlayer dielectric (ILD) layers onto a silicon wafer substrate. A passivation layer is deposited onto an outermost metal layer and at least a portion of the passivation layer is masked with a photoresist. A pit is etched through the photoresist in the substrate, said pit having a base and sidewalls. Etching is carried out along an edge of the substrate to expose the last metal layer to define bonding pads. A step of etching is carried out on either side of the pit to expose the outermost metal layer to define electrode portions. The bonding pads are for operatively connecting a microprocessor for controlling a heater element suspended in the pit between the electrode portions.

Abstract: Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.

Abstract: A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.

Abstract: A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.

Abstract: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano-tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric material to expose at least a portion of the CNT material; (5) fabricating a diode above the first conductor; and (6) fabricating a second conductor above the CNT material and the diode. Numerous other aspects are provided.

Abstract: Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods arc disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.

Abstract: A method for reducing dimension of an MEMS device. A single crystalline substrate having a diaphragm is provided. A first-step anisotropic dry etching process is performed to form an opening corresponding to the diaphragm in the back surface, the anisotropic dry etching stopping on a specific lattice plane extending from the edge of the diaphragm. A second-step anisotropic wet etching process is performed to etch the single crystalline substrate along the specific lattice plane until the diaphragm is exposed to form a cavity having a diamond-like shape.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.

Abstract: A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.

Abstract: A micro device having a micro system structure includes a protection film disposed on the micro system structure for protecting from a particle. The protection film includes a first protection film having a Vickers hardness equal to or larger than 2500 Hv or a nano indentation hardness equal to or larger than 13.64 GPa. The first protection film has a thickness in a range between 0.1 ?m and 30 ?m. The protection film has a total stress defined as a product of a film stress and a film thickness, and the total stress is equal to or smaller than 700 N/m.

Abstract: In a microminiature moving device that has disposed, on a single-crystal silicon substrate, movable elements (a movable rod 46, a movable comb electrode 49, etc.) displaceable in parallel to the substrate surface and stationary parts (a stationary part 40a, etc.), the stationary parts are fixedly secured to the single-crystal silicon substrate 61 with an insulating layer 62 sandwiched therebetween, and depressions 64 are formed in those surface regions of the single-crystal silicon substrate 61 where no stationary parts are present, and the movable parts are positioned above the depressions 64. The depressions 64 form gaps 50 large enough to prevent foreign bodies from causing troubles such as malfunction of the movable parts and shoring.

Abstract: Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack of one or more layers is formed over a substrate. The stack includes a layer of chalcogenide material and a metal, e.g., silver, containing layer. A protective layer is formed over the stack. The protective layer blocks light, is conductive, and is etch able with the other layers of the stack. Further, the metal of the metal containing layer is substantially insoluble in the protective layer. The stack and the protective layer are then patterned and etched to form memory elements.

Abstract: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures.

Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell region which is disposed on the semiconductor substrate and has a transistor array of a stacked gate structure having a floating gate, a Ti-containing barrier which is disposed in an upper layer of the memory cell region and covers the memory cell region, and a passivation layer disposed above the Ti-containing barrier.

Abstract: A method for fabricating a micro structure includes depositing a first layer of a first material over a substrate; patterning a first hard mask over the first layer; depositing a second layer of a second material over the first layer and the first hard mask; patterning a second hard mask over the second layer; and selectively removing the first material and the second material not covered by any of the first mask and the second mask to produce over the substrate the micro structure having a first structure portion having a first height and a second structure portion having a second height.

Abstract: A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface of the weight in the bottom surface of the recess portion 2 facing the same, an electrode 5 is formed. An alternating current electric power is applied between the weight portion 4 and the electrode 5 so that static electricity is created and the weight is excited by the static electricity. In an axial direction which is perpendicular to the direction of the excitation of the weight, an electrode 6 is disposed to face one surface of the weight and a wall surface of the substrate which faces the same. A change in a capacitance between the facing electrodes is electrically detected, and therefore, a change in a physical force acting in the same direction is detected.

Abstract: A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gate; depositing a nitride film and a first interlayer insulating film on the entire structure, etching a region of the first interlayer insulating film to form a source contact hole, forming a conductive film on the entire structure to bury the source contact hole, and polishing the conductive film; forming a second interlayer insulating film on the entire structure, and then etching the second and first interlayer insulating films and the nitride film using a mask through which regions in which a cell region and a drain contact will be formed are opened; and, forming a polysilicon layer on the entire structure.

Abstract: Disclosed are methods of fabricating a memory cell structure. More specifically, a copper substrate, including but not limited to copper contacts and/or bit lines, can be formed within a metal-containing layer, for example. Optionally, one or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. Copper sulfide material can be formed thereon. Alternatively, a portion of the exposed copper can be converted to copper sulfide (e.g., Cu2S2 or Cu2S). The copper sulfide material can then be exposed to a vapor phase monomer to facilitate selective growth of a conducting polymer.

Abstract: In a memory device and a method of forming a memory device, the device comprises a substrate, a first electrode extending in a vertical direction relative to the substrate, and a second electrode extending in a vertical direction relative to the substrate, the second electrode being spaced apart from the first electrode by a vertical gap. A third electrode is provided that extends in a vertical direction in the electrode gap, the third electrode being spaced apart from the first electrode by a first gap and the third electrode being spaced apart from the second electrode by a second gap, the third electrode being elastically deformable such that the third electrode deflects to be electrically coupled with the first electrode through the first gap in a first bent position and to be electrically coupled with the second electrode through the second gap in a second bent position, and to be isolated from the first electrode and the second electrode in a rest position.

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.

Abstract: The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel.

Abstract: A method of fabricating a suspended beam in a MEMS process, said method comprising the steps of: (a) etching a pit in a substrate, said pit having a base and sidewalls; (b) depositing sacrificial material on a surface of said substrate so as to fill said pit; (c) removing said sacrificial material from a perimeter region within said pit and from said substrate surface surrounding said pit; (d) reflowing remaining sacrificial material within said pit such that said remaining sacrificial material contacts said sidewalls; (e) depositing beam material on said substrate surface and on said reflowed sacrificial material; and (f) removing said reflowed sacrificial material to form said suspended beam.

Abstract: The invention relates to a sensor with at least one silicon-based micromechanical structure, which is integrated with a sensor chamber of a foundation wafer, and with at least one covering that covers the foundation wafer in the region of the sensor chamber, and to a method for producing a sensor.

Abstract: A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.

Abstract: A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate lines over a substrate, wherein the substrate is defined into a cell region and a peripheral region, forming a gate spacer layer over the gate lines, the gate spacer layer including a buffer layer, an insulation layer, and a barrier layer, forming a mask pattern over the barrier layer in a manner to cover the cell region and open the peripheral region, performing an anisotropic etching method on the gate spacer layer using the mask pattern as an etch mask to form gate spacers on sidewalls of the gate lines in the peripheral region, performing an ion implantation process to form source/drain regions in the peripheral region, and simultaneously removing the mask pattern and the barrier layer.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Abstract: A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.

Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.

Abstract: A micromechanical component having a substrate beneath at least one structured layer, in the structured layer at least one functional structure being formed, a cap which covers the functional structure, between the cap and the functional structure at least one cavity being formed, and a connecting layer which connects the cap to structured layer, as well as a method for producing the micromechanical component. To obtain a compact and robust component, the connecting layer is formed from an anodically bondable glass, i.e. a bond glass, which has a thickness in the range of 300 nm to 100 ?m, which may in particular be in the range of 300 nm to 50 ?m.