Abstract: In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

Abstract: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features.

Abstract: A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, source and drain electrodes directly on the semiconductor layer, each of the source and drain electrodes including at least one hole therethrough, a gate insulating layer on the substrate, and a gate electrode on the gate insulating layer and corresponding to the semiconductor layer.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract: A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

Abstract: Example embodiments provide a transistor and a method of manufacturing the same. The transistor may include a channel layer formed of an oxide semiconductor and a gate having a three-dimensional structure. A plurality of the transistors may be stacked in a perpendicular direction to a substrate. At least some of the plurality of transistors may be connected to each other.

Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract: A method of fabricating a liquid crystal display device includes forming first, second, and third active patterns on a substrate having a pixel region and a driving region, wherein the first and second active patterns are in the driving region and the third active pattern is in the pixel region, the first, second, and third active patterns each having an active region, a source region, and a drain region with the source and drain regions on opposing sides of the active region, forming a gate insulator on the first, second, and third active patterns, forming first, second, and third gate electrodes on the gate insulator, wherein the first, second, and third gate electrodes correspond to the active regions of the first, second, and third active patterns, respectively, doping the source and drain regions of the first, second, and third active patterns with n? ions using the first, second, and third gate electrodes as a doping mask, doping the n? doped source and drain regions of the second active pattern with p+

Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

Abstract: A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.

Abstract: Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

Abstract: A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.

Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

Abstract: A method for fabricating at least three different types of devices on a semiconductor substrate comprises forming a first electrode region and a second electrode region for a first semiconductor device at the same time as forming a first electrode region of a asymmetrical semiconductor device, and forming a first electrode region and a second electrode region for a second semiconductor device at the same time as forming a second electrode region of the asymmetrical semiconductor device.

Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.

Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.

Abstract: Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.

Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.

Abstract: The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching.

Abstract: A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

Abstract: A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract: Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer.

Abstract: When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

Abstract: A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.

Abstract: A vertical field effect transistor (FET) comprises a gate electrode and a first electrode layer having a dielectric layer interposed between these electrodes and a semiconducting active layer electrically coupled to the first electrode. The active layer and the dielectric layer sandwich at least a portion of the first electrode where at least one portion of the active layer is unshielded by the first electrode such that the unshielded portion is in direct physical contact with the dielectric layer. A second electrode layer is electrically coupled to the active layer where the second electrode is disposed on at least a portion of the unshielded portion of the active layer such that the second electrode can form electrostatic fields with the gate electrode upon biasing in unscreened regions near the first electrode.

Abstract: A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized.

Abstract: A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures.

Abstract: In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film is formed by oxidizing or nitriding the surface of an island-like semiconductor film, a semiconductor film is formed on a region which is a part of the insulating film, a gate electrode is formed over the insulating film, an impurity element imparting one conductivity type is added to the island-like semiconductor film and the semiconductor film using the gate electrode as a mask, the impurity element is activated by heating the island-like semiconductor film and the semiconductor film, and the part of the insulating film between the island-like semiconductor film and the semiconductor film disappears by heating the island-like semiconductor film and the semiconductor film.

Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.

Abstract: A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.

Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.

Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.

Abstract: First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.

Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.

Abstract: Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.