Source Or Drain Contact Programmed (epo) Patents (Class 257/E21.669)
  • Patent number: 8003971
    Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 23, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7915688
    Abstract: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 7514756
    Abstract: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: April 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi