Entire Channel Doping Programmed (epo) Patents (Class 257/E21.672)
  • Patent number: 11322355
    Abstract: Some embodiments of the disclosure provide a method for forming a semiconductor device. The method includes: forming a plurality of semiconductor material layers on a doped substrate; removing a part of the plurality of semiconductor material layers to form an exposed doped substrate; and ion implanting a dopant into the exposed doped substrate to form a doped semiconductor structure, where the doped substrate and the doped semiconductor structure have different polarities.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 3, 2022
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Qiyue Zhao, Chuan He
  • Patent number: 10777517
    Abstract: An apparatus with a body layer disposed over a substrate is disclosed. The body layer has first and second diffusion areas with a first current collection area between the two. A plurality of first drain/source (D/S) diffusions spaced parallel with one another resides within the first diffusion area. A plurality of first channel regions resides within the first diffusion area such that each of the plurality of first channel regions resides between an adjacent pair of the plurality of the first D/S diffusions. A plurality of second D/S diffusions resides within the second diffusion area and are spaced parallel with one another. A plurality of second channel regions reside within the second diffusion area such that each of the plurality of second channel regions resides between an adjacent pair of the plurality of the second D/S diffusions. A first current collection diffusion resides within the first current collection area.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Padmmasini Desikan
  • Patent number: 10528932
    Abstract: A method and system for generating a document is provided. The method includes generating a metadocument configured to retain multiple components of different data types. A component editor directory of a component editor server is queried and a list of component editors compatible with metadocument is retrieved. A first component editor of the list of component editors is selected from a remote location. The first component editor is associated with a first defined data type. A first document component comprising the first defined data type is generated within the metadocument resulting in a single document comprising the first document component. A user interface is updated with the single document comprising the first document component.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventor: Michael Sean Brown
  • Patent number: 9991121
    Abstract: To improve accuracy and shielding capabilities of impurity implantation, a method of manufacturing a semiconductor device is provided, the method including forming a first photoresist on a front surface of a semiconductor substrate, the front surface being provided with a front surface structure, forming, on the first photoresist or below a rear surface of the semiconductor substrate, a second photoresist having opposite photo-curing properties from those of the first photoresist, and implanting impurities into the semiconductor substrate using as a mask the second photoresist, which has been subjected to patterning.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 5, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiko Kajiwara
  • Patent number: 9805818
    Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-seong Kim, Cheol-ha Lee
  • Patent number: 9786508
    Abstract: The present disclosure provides semiconductor devices and fabrication methods thereof. A work function layer is formed on the semiconductor substrate. A buffer layer is formed on the work function layer. The work function layer is doped through the buffer layer with impurity ions. The buffer layer obstructs a flow of the impurity ions to control a concentration of the impurity ions in different regions of the work function layer to regulate a work function of the work function layer in the different regions.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 10, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 9646872
    Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 9620216
    Abstract: The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 11, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 7824988
    Abstract: A method includes forming a source, a drain, and a disposable gate (38) of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable gates of the first transistor and the second transistor; forming a photoresist layer over the first transistor and the second transistor; patterning the photoresist layer to expose a gate region of the first transistor and a gate region of the second transistor; and implanting the substrate under the gate region of the first transistor and under the gate region of the second transistor, wherein implanting the substrate under the gate region of the first transistor provides a permanent shorting region between the source and the drain of the first transistor, and wherein implanting the substrate under the gate region of the second transistor adjusts a threshold voltage of the second transistor.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander Hoefler, James D. Burnett, Lawrence N. Herr