With Source And Drain On Different Levels, E.g., Sloping Channel (epo) Patents (Class 257/E21.692)
  • Patent number: 9006793
    Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
  • Patent number: 8012819
    Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiaoxin Zhang, Wenxu Xianyu, Takashi Noguchi, Hans S. Cho, Huaxiang Yin
  • Patent number: 7948017
    Abstract: A method of forming an imaging array includes providing a single crystal silicon substrate having an internal separation layer, forming a patterned conductive layer proximate a first side of the single crystal silicon substrate, forming an electrically conductive layer on the first side of the single crystal silicon substrate and in communication with the patterned conductive layer, securing the single crystal silicon substrate having the patterned conductive layer and electrically conductive layer formed thereon to a glass substrate with the first side of the single crystal silicon substrate proximate the glass substrate, separating the single crystal silicon substrate at the internal separation layer to create an exposed surface opposite the first side of the single crystal silicon substrate and forming an array comprising a plurality of photosensitive elements and readout elements on the exposed surface.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 24, 2011
    Assignee: Carestream Health, Inc.
    Inventors: Timothy J. Tredwell, Jackson Lai
  • Patent number: 7923326
    Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: April 12, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heung Jin Kim
  • Patent number: 7847342
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 7709380
    Abstract: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 4, 2010
    Assignee: IMEC
    Inventor: Anabela Veloso
  • Patent number: 7704834
    Abstract: Disclosed is a method for forming a non-volatile memory device, comprising the steps of: successively depositing a gate oxide and a floating gate material on a semiconductor substrate; depositing and selectively etching a first dielectric on the floating gate material to form a first dielectric pattern; forming a first floating gate oxide on the floating gate material; selectively etching the floating gate material with using the first dielectric pattern as a mask to form a floating gate pattern; forming an insulating layer on the floating gate pattern; etching a portion of the semiconductor substrate between neighboring floating gate patterns to form a trench in the substrate; depositing a control gate oxide on surfaces of the trench; depositing a control gate material to fill the trench and to cover the substrate surface; depositing a second dielectric on the control gate material; selectively etching the second dielectric and the control gate material to form a control gate pattern and a second dielectric
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 27, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Heong Jin Kim
  • Publication number: 20090146206
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.
    Type: Application
    Filed: November 28, 2008
    Publication date: June 11, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20090146190
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 11, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka