Substrate Is Nonsemiconductor Body, E.g., Insulating Body (epo) Patents (Class 257/E21.704)
  • Publication number: 20110309334
    Abstract: A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
  • Publication number: 20110309333
    Abstract: A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20110309332
    Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 22, 2011
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
  • Publication number: 20110303980
    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Akif SULTAN, Indradeep SEN
  • Publication number: 20110291169
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Publication number: 20110291193
    Abstract: A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: Andres Bryant, Josephine B. Chang, Jeffrey W. Sleight
  • Publication number: 20110279201
    Abstract: The invention relates to temperature compensated micro-electro-mechanical (MEMS) resonators (300) preferably made of silicon. Prior art MEMS resonators have a significant temperature coefficient of resonance frequency, whereby it is difficult to achieve a sufficiently good frequency stability. The inventive MEMS resonator has a resonance plate (310) which resonates in Lamé mode. The resonance plate is p+ doped material, such as silicon doped with boron, and the concentration of the p+ doping is such that the plate has a temperature coefficient of resonance frequency near to zero. The tensile stress and the second order temperature coefficient can further be reduced by doping the plate with germanium.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: VALTION TEKNILLINEN TUTKIMUSKESKUS
    Inventors: Tuomas PENSALA, Antti JAAKKOLA
  • Patent number: 8039838
    Abstract: Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: October 18, 2011
    Assignee: Soligie, Inc.
    Inventors: John M. Heitzinger, John Snyder
  • Patent number: 8039911
    Abstract: The MEMS sensor according to the present invention includes a diaphragm. In the diaphragm, an angle formed by two straight lines connecting supporting portions and the center of a main portion with one another respectively is set to satisfy the relation of the following formula (1): (A2/A1)/(B2/B1)?1??(1) A2: maximum vibrational amplitude of the diaphragm in a case of working a physical quantity of a prescribed value on the diaphragm A1: maximum vibrational amplitude of the diaphragm in a case of working the physical quantity on the diaphragm in an omitting structure obtained by omitting one of the supporting portions from the diaphragm B2: maximum stress caused in the diaphragm in the case of working the physical quantity on the diaphragm B1: maximum stress caused in the diaphragm in the case of working the physical quantity on the diaphragm in the omitting structure.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: October 18, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Mizuho Okada, Nobuhisa Yamashita
  • Publication number: 20110204444
    Abstract: A semiconductor integrated device of the invention can enhance a radiation resistance. In an exemplary embodiment, the semiconductor integrated device includes a semiconductor supporting substrate, an insulation layer provided on the semiconductor supporting substrate, and a silicon thin film provided on the insulation layer. A predetermined region in the silicon thin film that is adjacent to the boundary between the insulation layer and the silicon thin film (i.e., boundary neighboring region) has an impurity-concentration-increased region. In this region, the impurity concentration becomes higher as the position approaches the boundary.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 25, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Publication number: 20110198592
    Abstract: Disclosed are a thin film transistor having high reliability and providing a simplified fabricating process, and a method of fabricating the thin film transistor. In the method, a dielectric substrate is prepared, a semiconductor layer is formed on the dielectric substrate, a gate dielectric film is formed on the semiconductor layer, a first gate electrode is formed on the gate dielectric film, a second gate electrode contacting a side wall of the first gate electrode is formed, and impurities are implanted into the semiconductor layer using the first gate electrode as a mask.
    Type: Application
    Filed: June 4, 2010
    Publication date: August 18, 2011
    Applicant: SNU R&DB FOUNDATION
    Inventors: Sun Jae Kim, Min Koo Han
  • Publication number: 20110180862
    Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, John E. Barth, JR., Herbert L. Ho, Edward J. Nowak, Wayne Trickle
  • Patent number: 7986000
    Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a secon
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
  • Publication number: 20110175164
    Abstract: A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Huiming Bu, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Ali Khakifirooz, Devendra K. Sadana, Chun-chen Yeh
  • Publication number: 20110175152
    Abstract: An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, JR., Kangguo Cheng, Bruce B. Doris, Ghavam G. Shahidi
  • Publication number: 20110169089
    Abstract: An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20110169084
    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bin YANG, Rohit PAL, Michael HARGROVE
  • Publication number: 20110169083
    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bin YANG, Rohit PAL, Michael HARGROVE
  • Patent number: 7977173
    Abstract: Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: July 12, 2011
    Assignee: Soligie, Inc.
    Inventors: John M. Heitzinger, John Snyder
  • Publication number: 20110163382
    Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio L. P. Rotondaro
  • Publication number: 20110163383
    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 7, 2011
    Applicant: International Business Machines Corporation
    Inventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
  • Publication number: 20110147840
    Abstract: A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Stephen M. Cea, Rishabh Mehandru, Lucian Shifren, Kelin Kuhn
  • Publication number: 20110140094
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed.
    Type: Application
    Filed: June 24, 2010
    Publication date: June 16, 2011
    Inventors: Tae-Young Choi, Hi-Kuk Lee, Bo-Sung Kim, Young-Min Kim, Seung-Hwan Cho, Young-Soo Yoon, Yeon-Taek Jeong, Seon-Pil Jang
  • Patent number: 7955940
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
  • Publication number: 20110101500
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Publication number: 20110101302
    Abstract: Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 5, 2011
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Chongwu Zhou, Chuan Wang, Jialu Zhang, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco
  • Publication number: 20110095294
    Abstract: A thin film transistor array panel includes: an insulation substrate; a gate line disposed on the insulation substrate and including a compensation pattern protruding from the gate line; a first data line and a second data line both intersecting the gate line; a first thin film transistor connected to the gate line and the first data line; a second thin film transistor connected to the gate line and the second data line; and a first pixel electrode and a second pixel electrode connected to the first thin film transistor and the second thin film transistor, respectively. The first pixel electrode and the second pixel electrode share the compensation pattern.
    Type: Application
    Filed: September 3, 2010
    Publication date: April 28, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun LEE, Yeo-Geon YOON, Hyoung-Wook LEE, Mi-Ae LEE
  • Publication number: 20110049594
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
  • Publication number: 20110049518
    Abstract: An object is to prevent contamination of a semiconductor film in a transistor or a semiconductor device including the transistor. Another object is to suppress variation in electrical characteristics and deterioration. A transistor including: a gate electrode layer provided over a substrate; a gate insulating film provided over the gate electrode layer; a semiconductor layer which is provided over the gate insulating film and which overlaps the gate electrode layer; a carbide layer provided over and in contact with a surface of the semiconductor layer; and a source electrode layer and a drain electrode layer which are electrically connected to the semiconductor layer is provided.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kosei Noda
  • Publication number: 20110049627
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: LELAND CHANG, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20110037125
    Abstract: A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ghavam G. Shahidi
  • Publication number: 20110032444
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Masayuki SAKAKURA, Yoshiaki OIKAWA, Kenichi OKAZAKI, Hotaka MARUYAMA, Masashi TSUBUKU
  • Publication number: 20110031497
    Abstract: One object of the present invention is to increase an aperture ratio of a semiconductor device. A pixel portion and a driver circuit are provided over one substrate. The first thin film transistor (TFT) in the pixel portion includes: a gate electrode layer over the substrate; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; source and drain electrode layers over the oxide semiconductor layer; over the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, a protective insulating layer which is in contact with part of the oxide semiconductor layer; and a pixel electrode layer over the protective insulating layer. The pixel portion has light-transmitting properties. Further, a material of source and drain electrode layers of a second TFT in the driver circuit is different from a material of those of the first TFT.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Miyuki HOSOBA, Eriko NISHIDA
  • Publication number: 20110031490
    Abstract: A method is proposed for producing a thin-film transistor (TFT), the method comprising forming a substrate, applying a ZnO-based precursor solution onto the substrate to form a ZnO-based channel layer, annealing the channel layer, forming a source electrode and a drain electrode on the channel layer, forming a dielectric layer on the channel layer and forming a gate electrode on the dielectric layer.
    Type: Application
    Filed: July 28, 2010
    Publication date: February 10, 2011
    Applicant: SONY CORPORATION
    Inventors: CHUNMEI WANG, WEI BENG NG, TAKEHISA ISHIDA
  • Publication number: 20110031552
    Abstract: To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Inventors: Toshiaki IWAMATSU, Kozo Ishikawa, Kiyoshi Hayashi
  • Publication number: 20110031498
    Abstract: A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. Each of the layers of the first thin film transistor has a light-transmitting property. Materials of the gate electrode layer, the source electrode layer and the drain electrode layer of the first thin film transistor are different from those of the second transistor, and each of the resistances of the second thin film transistor is lower than that of the first thin film transistor.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hajime Kimura, Hiroki Ohara, Masayo Kayama
  • Publication number: 20110024751
    Abstract: In a bottom-gate thin film transistor using the stack of the first oxide semiconductor layer and the second oxide semiconductor layer, an oxide insulating layer serving as a channel protective layer is formed over and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the insulating layer, an oxide insulating layer covering a peripheral portion (including a side surface) of the stack of the oxide semiconductor layers is formed.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Masashi TSUBUKU, Toshinari SASAKI, Hideaki KUWABARA
  • Publication number: 20110024750
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hiroki OHARA, Toshinari SASAKI, Kosei NODA, Hideaki KUWABARA
  • Publication number: 20110017995
    Abstract: An object is to increase the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a channel-etched thin film transistor for a driver circuit, in which a source electrode and a drain electrode are formed using a metal and a channel layer is formed using an oxide semiconductor, and a driver circuit wiring formed using a metal. The display portion includes a channel protection thin film transistor for a pixel, in which a source electrode and a drain electrode are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor, and a display portion wiring formed using an oxide conductor. The thin film transistors provided in the semiconductor device are formed with a resist mask formed using a multi-tone mask.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 27, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroyuki MIYAKE, Hideaki KUWABARA, Ikuko KAWAMATA
  • Publication number: 20110012199
    Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: IO SEMICONDUCTOR, INC.
    Inventors: Paul A. Nygaard, Stuart B. Molin, Michael A. Stuber
  • Publication number: 20110012116
    Abstract: A highly reliable display device which has high aperture ratio and includes a transistor with stable electrical characteristics is manufactured. The display device includes a driver circuit portion and a display portion over the same substrate. The driver circuit portion includes a driver circuit transistor and a driver circuit wiring. A source electrode and a drain electrode of the driver circuit transistor are formed using a metal. A channel layer of the driver circuit transistor is formed using an oxide semiconductor. The driver circuit wiring is formed using a metal. The display portion includes a pixel transistor and a display portion wiring. A source electrode and a drain electrode of the pixel transistor are formed using a transparent oxide conductor. A semiconductor layer of the pixel transistor is formed using the oxide semiconductor. The display portion wiring is formed using a transparent oxide conductor.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroyuki MIYAKE, Hideaki KUWABARA
  • Publication number: 20110012669
    Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: IO SEMICONDUCTOR, INC.
    Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
  • Publication number: 20110012117
    Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroyuki MIYAKE, Hideaki KUWABARA
  • Publication number: 20110012118
    Abstract: An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroyuki MIYAKE, Hideaki KUWABARA, Hideki UOCHI
  • Publication number: 20110001191
    Abstract: A semiconductor device which includes: a semiconductor layer formed over an insulating layer over a semiconductor substrate; a gate electrode disposed over the semiconductor layer through a gate insulator; a sidewall insulator formed along the gate insulating film and a sidewall of the gate electrode; a source/drain layer including an alloy layer whose bottom surface is in contact with the insulating layer; and an impurity-doped layer which is segregated in a self-aligned manner in an interface between the alloy layer and the semiconductor layer and has a face for junction with a channel region formed along a crystal orientation plane of the semiconductor layer.
    Type: Application
    Filed: July 5, 2010
    Publication date: January 6, 2011
    Inventors: Akio SHIMA, Nobuyuki SUGII
  • Publication number: 20100327358
    Abstract: The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Stephan Kronholz, Roman Boschke, Vassilios Papageorgiou, Maciej Wiatr
  • Publication number: 20100323482
    Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Inventors: Young Seok CHOI, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Publication number: 20100315583
    Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 16, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Lin Lin, Ching-Huan Lin, Chih-Hung Shih, Wei-Ming Huang, Chih-Hung Lin, Yu-Cheng Chen, Yi-Hui Li, Tsan-Chun Wang
  • Publication number: 20100317163
    Abstract: A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body.
    Type: Application
    Filed: March 26, 2010
    Publication date: December 16, 2010
    Inventor: John J. Seliskar
  • Publication number: 20100311212
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. the semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit.
    Type: Application
    Filed: July 28, 2010
    Publication date: December 9, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai