Substrate Is Nonsemiconductor Body, E.g., Insulating Body (epo) Patents (Class 257/E21.704)
  • Publication number: 20080299742
    Abstract: There is disclosed a method for manufacturing an SOI wafer comprising: a step of implanting at least one of a hydrogen ion and a rare gas ion into a donor wafer to form an ion implanted layer; a step of bonding an ion implanted surface of the donor wafer to a handle wafer; a step of delaminating the donor wafer at the ion implanted layer to reduce a film thickness of the donor wafer, thereby providing an SOI layer; and a step of etching the SOI layer to reduce a thickness of the SOI layer, wherein the etching step includes: a stage of performing rough etching as wet etching; a stage of measuring a film thickness distribution of the SOI layer after the rough etching; and a stage of performing precise etching as dry etching based on the measured film thickness distribution of the SOI layer. There can be provided A method for manufacturing an SOI wafer having high film thickness uniformity of an SOI layer with excellent productivity.
    Type: Application
    Filed: May 20, 2008
    Publication date: December 4, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Publication number: 20080265348
    Abstract: A method of manufacturing a back-side (14) illuminated image sensor (1) is disclosed, comprising the steps of: starting with a wafer (2) having a first (3) and a second surface (4), providing light sensitive pixel regions (5) extending into the wafer (2) from the first surface (3), securing the wafer (2) onto a protective substrate (7) such that the first surface (3) faces the protective substrate, the wafer comprising a substrate of a first material (8) with an optical transparent layer (9) and a layer of semiconductor material (10), wherein the substrate (8) is selectively removed from the layer of semiconductor material by using the optical transparent layer (9) as stopping layer. For back-side illuminated image sensors, light has to transmit through the semiconductor layer and enter into the light sensitive pixel regions (5). In order to reduce absorption losses, it is very advantageous that the semiconductor layer (10) can be made relatively thin with a good uniformity.
    Type: Application
    Filed: May 12, 2005
    Publication date: October 30, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Joris Maas, Leendert De Bruin, Daniel Wilhelmus Elisabeth Verbugt, Nicolaas Johannes Anthonius Van Veen, Eric Cornelis Egbertus Van Grunsven, Gerardus Lubertus Jacobus Reuvers, Erik Harold Groot
  • Publication number: 20080268621
    Abstract: The invention relates to methods for manufacturing compound material wafers, in particular silicon on insulator wafers, by the steps of providing a donor substrate, forming an insulating layer, providing a handle substrate, creating a predetermined splitting area in the donor substrate, attaching the donor substrate to the handle substrate and detaching at the predetermined splitting area to achieve the compound material wafer. In order to be able to more often reuse the remainder of the donor substrate in subsequent manufacturing runs, various embodiments are disclosed, such as the insulating layer can be provided on the donor substrate at a maximum thickness of 500 A, or that the insulating layer can be provided by deposition or only upon the handle substrate. Alternatively, no insulating layer is provided so that the donor and handle substrates can have different crystal orientations.
    Type: Application
    Filed: September 5, 2007
    Publication date: October 30, 2008
    Inventors: Patrick Reynaud, Oleg Kononchuk
  • Patent number: 7442585
    Abstract: The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 28, 2008
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Xiangdong Chen
  • Publication number: 20080261381
    Abstract: When manufacturing a bonded substrate using an insulator substrate as a handle wafer, there is provided a method for manufacturing a bonded substrate which can be readily removed after carried and after mounted by roughening a back surface of the bonded substrate (corresponding to a back surface of the insulator substrate) and additionally whose front surface can be easily identified like a process of a silicon semiconductor wafer in case of the bonded substrate using a transparent insulator substrate as a handle wafer. There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a back surface of the insulator substrate.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 23, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 7419878
    Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: September 2, 2008
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Publication number: 20080206951
    Abstract: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
    Type: Application
    Filed: May 5, 2008
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Judson R. Holt, Qiqing C. Ouyang
  • Patent number: 7410913
    Abstract: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 12, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hyun Lee, Sang-Bong Bang
  • Patent number: 7411250
    Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: August 12, 2008
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Anthony M. Miscione, George Imthurn, Eugene F. Lyons, Michael A. Stuber
  • Patent number: 7410841
    Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: August 12, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Howard Lee Tigelaar
  • Publication number: 20080179636
    Abstract: The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
    Type: Application
    Filed: January 27, 2007
    Publication date: July 31, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta, David M. Onsongo, Carl J. Radens
  • Publication number: 20080153278
    Abstract: An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure.
    Type: Application
    Filed: March 6, 2008
    Publication date: June 26, 2008
    Applicant: International Business Machines Corporation
    Inventors: Edward J. Nowak, Jed H. Rankin, William R. Tonti, Richard Q. Williams
  • Patent number: 7390702
    Abstract: Laser is applied onto part on an SOS substrate using a sapphire layer to form an identifying mark. The sapphire layer on the surface of the SOS substrate, which has been exposed upon laser application, is covered with an insulating film formed by heat treatment at 700° C. or less, and thereafter a device is formed using heat treatment at a temperature higher than 700° C.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: June 24, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshiyuki Nakamura
  • Publication number: 20080135875
    Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
    Type: Application
    Filed: February 14, 2008
    Publication date: June 12, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
  • Publication number: 20080122042
    Abstract: A wafer comprising polycrystalline silicon is used in various applications, including as a handling wafer, a test wafer, a dummy wafer, or as a substrate in a bonded die. Use of polycrystalline material instead of single-crystal may lower expenses.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: Michael Goldstein, Irwin Yablok
  • Patent number: 7361534
    Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: April 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mario M. Pelella
  • Publication number: 20080067562
    Abstract: A semiconductor device includes a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate and a constituent of the semiconductor layer including a nitride semiconductor different from a constituent of the substrate, a via hole provided in the substrate and configured to extend from a rear surface side of the substrate to the semiconductor layer, a ground electrode formed on an inner wall of the via hole, a contact layer provided in the semiconductor layer and configured to extend from a surface of the semiconductor layer to the ground electrode, a gate electrode and a drain electrode, each of which being formed on the semiconductor layer, and a source electrode formed on the semiconductor layer and connected to the ground electrode through the contact layer.
    Type: Application
    Filed: August 15, 2007
    Publication date: March 20, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hisao KAWASAKI
  • Publication number: 20080057618
    Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
    Type: Application
    Filed: August 23, 2007
    Publication date: March 6, 2008
    Inventors: Tatsuya Honda, Yasuyuki Arai
  • Publication number: 20080044959
    Abstract: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.
    Type: Application
    Filed: October 26, 2007
    Publication date: February 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Louis Hsu, Jack Mandelman
  • Publication number: 20080042137
    Abstract: An electro-optical device includes a substrate having a display region; TFTs each including a first electrode in the display region, a first insulating layer on the first electrode, a second electrode on the first insulating layer, and a second insulating layer on the second electrode; and terminals each including a first metal on a protruding section extending from the display region, which is located at the same level and made of the same metal as the first electrode, a second metal which is located at the same level and made of the same metal as the second electrode, and which partly overlaps the first metal in plan view, and a portion of the first insulating layer. The first insulating layer separates the first and second metals and the first metal is electrically connected to the first electrode or the second metal is electrically connected to the second electrode.
    Type: Application
    Filed: April 27, 2007
    Publication date: February 21, 2008
    Applicant: EPSON IMAGING DEVICES CORPORATION
    Inventors: Masahiro HORIGUCHI, Hideki KANEKO
  • Publication number: 20080044956
    Abstract: An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in a predetermined direction in such a condition that the substrate and the nozzle system face each other, (c) a filter system which filters off particles out of the acid solution having been sprayed onto the substrate, and (d) a circulation system which circulates the acid solution having been sprayed onto the substrate, to the filter system, and further, to the nozzle system from the filter system.
    Type: Application
    Filed: July 2, 2007
    Publication date: February 21, 2008
    Applicant: NEC Corporation
    Inventor: Kazushige Takechi
  • Publication number: 20080044965
    Abstract: A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film to change the amorphous silicon film to a polycrystalline silicon film; removing the metal plate and the sacrificial film; patterning the polycrystalline silicon film to form a semiconductor; forming a gate insulating layer which covers the semiconductor; forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor; heavily doping a conductive impurity into portions of the semiconductor to form a source region and a drain region; forming an interlayer insulating layer which covers the gate line and the semiconductor; and forming a data line and an output electrode connected to the source and drain regions, respectively, on the
    Type: Application
    Filed: August 16, 2007
    Publication date: February 21, 2008
    Applicants: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae-Beom CHOI, Young-Jin CHANG, Yoon-Seok CHOI, Seung-Hwan SHIM, Han-Na JO, Jung-Hoon SHIN, Joon-Young KOH
  • Publication number: 20080036002
    Abstract: Surge current, which flows-in from an exterior due to ESD or the like, is prevented from directly flowing-into a supporting substrate. A semiconductor device has: an element-isolating insulating film sectioning an SOI layer into an active region and a field region; a resistance element formed at the field region; one or more layers of an interlayer insulating films formed on an SOI substrate; a ground terminal for a substrate contact formed on the interlayer insulating film; a substrate contact passing through the element-isolating insulating film and a BOX layer, and electrically connected to the supporting substrate; a first wire electrically connecting the substrate contact and the resistance element; and a second wire electrically connecting the resistance element and the ground terminal for a substrate contact.
    Type: Application
    Filed: June 19, 2007
    Publication date: February 14, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Koichi Kishiro
  • Publication number: 20080032467
    Abstract: In some embodiments, a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor) and methods for manufacturing such a chip. The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip.
    Type: Application
    Filed: October 10, 2007
    Publication date: February 7, 2008
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Vladislav Vashchenko, Peter Hopper, Yuri Mirgorodski
  • Publication number: 20080026511
    Abstract: A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer which can be etched faster than a semiconductor substrate, on the semiconductor substrate including a first region that is arranged at a predetermined interval and is to be provided with a silicon on insulator (SOI) structure; b) forming a second semiconductor layer etched slower than the first semiconductor layer, on the first semiconductor layer; c) removing the first semiconductor layer and the second semiconductor layer from a second region which is adjacent to the first region via one line and disposed singly to each of the first region, so as to form a recess that exposes the semiconductor substrate, for a support; d) forming a support precursor layer made of insulating material on a region including at least the first region and the second region on the semiconductor substrate; e) etching and removing the support precursor layer except for a part thereof corresponding to the first region and corresponding
    Type: Application
    Filed: June 19, 2007
    Publication date: January 31, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Kei Kanemoto
  • Publication number: 20080017923
    Abstract: The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 24, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Publication number: 20080001156
    Abstract: In a case where a p-channel thin film transistor is used as a thin film transistor that is electrically connected to a light-emitting element and drives the light-emitting element, a value of cutoff current of the p-channel thin film transistor is made lower than that of a p-channel thin film transistor of a driver circuit. Specifically, channel doping is selectively performed on a semiconductor layer of a thin film transistor included in a pixel.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 3, 2008
    Inventors: Masayuki Sakakura, Hiroyuki Miyake
  • Publication number: 20070290263
    Abstract: It is made possible to obtain epitaxially grown layers with excellent crystallinity. A semiconductor device includes: a semiconductor layer having crystallinity; a first insulating film formed on the semiconductor layer and having a first opening to reach the semiconductor layer; a first epitaxially grown layer formed on the first insulating film so as to embed the first opening; a second insulating film formed on the first epitaxially grown layer and having a second opening to reach the first epitaxially grown layer; and a second epitaxially grown layer formed on the second insulating film so as to embed the second opening.
    Type: Application
    Filed: March 7, 2007
    Publication date: December 20, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiki KAMATA
  • Publication number: 20070262384
    Abstract: A semiconductor device comprising a high breakdown voltage transistor and a low breakdown voltage transistor. The semiconductor device comprises a support substrate, an insulating layer formed on the support substrate, a high breakdown voltage transistor, a low breakdown voltage transistor, wherein the high breakdown voltage transistor is adjacent to a first isolation region having a depth that reaches the insulating layer, and the low breakdown voltage transistor is adjacent to a second isolation region having a depth that does not reach the insulating layer.
    Type: Application
    Filed: June 4, 2007
    Publication date: November 15, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Yoko Sato
  • Patent number: 7291521
    Abstract: A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 6, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Yasuhito Shiho
  • Publication number: 20070231977
    Abstract: A method of fabricating a thin film transistor includes forming an active layer on an insulating substrate; forming a gate insulation film on the insulating substrate; forming source, drain, and body contact regions which are separated by a channel region in the active layer; forming a gate on the gate insulation film; forming an interlayer insulation film on the insulating substrate; and forming source and drain electrodes electrically connected with the source and drain regions, respectively, wherein a voltage is applied to the channel region of the active layer through the body contact region, and the body contact region is connected to the source or drain electrode.
    Type: Application
    Filed: June 11, 2007
    Publication date: October 4, 2007
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Byoung-Deog CHOI, Sung-Sik Bae, Won-Sik Kim
  • Publication number: 20070231982
    Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.
    Type: Application
    Filed: June 4, 2007
    Publication date: October 4, 2007
    Applicant: AU OPTRONICS CORP.
    Inventors: Hui-Chang Chen, Chun-Yu Lee, Shih-Ping Chou
  • Publication number: 20070212828
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material.
    Type: Application
    Filed: May 4, 2007
    Publication date: September 13, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura
  • Patent number: 7064021
    Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: June 20, 2006
    Assignee: AU Optronics Corp.
    Inventor: Chih-Chin Chang