Abstract: A carrier comprises: a main body made of a material comprising a thermal conductivity of at least 380 W/(m K), wherein the main body comprises a mounting surface for mechanical and thermal connection with a component, wherein the main body comprises a recess which penetrates the main body along a first direction perpendicular to the main extension plane of the main body, an electrically insulating filler is arranged in the recess, which comprises a further recess penetrating the filler along the first direction, an inner wall of the filler surrounding the further recess is provided with an electrically conductive coating to form a via through the main body.

Abstract: Provided is an insulating sheet capable of effectively enhancing thermal conduction and adhesiveness. The insulating sheet according to the present invention contains a thermosetting component and a thermally conductive filler, the thermally conductive filler contains boron nitride, the insulating sheet has a first surface on one side in a thickness direction and a second surface on the other side in the thickness direction, and a first content of the boron nitride in 100% by volume of a region having a thickness of 10% of a thickness of the sheet, from the first surface toward the second surface is smaller than a second content of the boron nitride in 100% by volume of a region having a thickness of 90% of a thickness of the sheet, from the second surface toward the first surface.

Abstract: A method for providing a part with a plasma resistant ceramic coating for use in a plasma processing chamber is provided. A patterned mask is placed on the part. A film is deposited over the part. The patterned mask is removed. A plasma resistant ceramic coating is applied on the part.

Abstract: An electronic element mounting substrate includes a first substrate including a first main surface and a mounting portion in a rectangular shape for mounting an electronic element, positioned on the first main surface and one end portion of the mounting portion in a longitudinal direction being positioned at an outer edge portion of the first main surface and a second substrate positioned on a second main surface opposite to the first main surface, formed of a carbon material, and including a third main surface facing the second main surface and a fourth main surface opposite to the third main surface. A thermal conduction of the mounting portion in a direction perpendicular to in a longitudinal direction is greater than a thermal conduction of the mounting portion in the longitudinal direction, in the third main surface or the fourth main surface, in plan view.

Abstract: A semiconductor package device includes a lead frame including a lead frame pad and lead frame leads, a semiconductor chip located on the lead frame pad, and a substrate located on the semiconductor chip, wherein the lead frame leads include first lead frame leads coupled to the lead frame pad and second lead frame leads separated from the lead frame pad and attached to a bottom surface of the substrate.

Abstract: Methods for making a tribological bearing wear surface for a compressor component are provided. Such methods involve semi-solid metal casting, where an admixture of solid lubricant particles and a metal alloy material is heated to melt the metal alloy material, while the lubricant particles remain in a solid phase. The alloy material and solid lubricant have substantially different densities. The metal alloy material may be a copper, iron, or aluminum alloy, for example. The method further comprises mixing and cooling the admixture to form a semi-solid slurry admixture. Next, the method comprises introducing the semi-solid slurry admixture into a die. Finally, the semi-solid slurry admixture in the die is solidified to form a solid component having the solid lubricant particles homogenously distributed within a metal alloy material matrix, thus forming a metal matrix composite. Compressor components made from such methods are also provided.

Abstract: An aerosol delivery device is provided, and includes a control body serially engaged with a cartridge, the cartridge having an aerosol precursor source housing an aerosol precursor and defining a mouth opening configured to direct an aerosol therethrough to a user. A heater device is operably engaged with the cartridge, wherein the heater device comprises an electrically-conductive carbon element disposed adjacent to a heat-conductive substrate. The heater device is configured to receive the aerosol precursor from the aerosol precursor source onto the heat-conductive substrate, such that the aerosol precursor on the heat-conductive substrate forms the aerosol in response to heat from the electrically-conductive carbon element conducted through the heat-conductive substrate. An associated apparatus and method are also provided.

Abstract: Provided is a bonding joining structure in which a heat generating body and a support including a metal are joined to each other via a joint portion composed of a sintered body of copper powder. The support contains copper or gold, the copper or gold being present in at least an outermost surface of the support. An interdiffusion portion in which copper or gold contained in the support and copper contained in the sintered body is formed so as to straddle a bonding interface between the support and the sintered body. Preferably, a copper crystal structure having the same crystal orientation is formed in the interdiffusion portion so as to straddle the bonding interface.

Abstract: Methods for forming a diamond like carbon layer with desired film density, mechanical strength and optical film properties are provided. In one embodiment, a method of forming a diamond like carbon layer includes generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, and forming a diamond like carbon layer on the surface of the substrate. The diamond like carbon layer is formed by an electron beam plasma process, wherein the diamond like carbon layer serves as a hardmask layer in an etching process in semiconductor applications. The diamond like carbon layer may be formed by bombarding a carbon containing electrode disposed in a processing chamber to generate a secondary electron beam in a gas mixture containing carbon to a surface of a substrate disposed in the processing chamber, and forming a diamond like carbon layer on the surface of the substrate from elements of the gas mixture.

Abstract: A method and an assembly for production of a mechanical component by sintering a pulverulent material, the method including: providing a pulverulent metallic material including grains, the pulverulent metallic material having a determined melting temperature; agglomerating a given quantity of the pulverulent metallic material under pressure inside a cavity; providing thermal energy to the given quantity of pulverulent metallic material to bring it to a given temperature below the melting temperature; and shocking the given quantity of agglomerated pulverulent metallic material and brought to the given temperature to bind the grains of the pulverulent metallic material to each other to obtain one solid body. The one solid body is thus maintained under pressure and thermal energy accumulated in the solid body is made to dissipate to obtain the mechanical component.

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

Abstract: A process for manufacturing a multilayer timepiece component, wherein it comprises the following steps: E1, E2: manufacturing at least one first metal layer (13) of the timepiece component on the upper surface of a substrate (10); E13: separating the substrate (10) from the structure obtained by the preceding step, in order to obtain a sheet; then E4, E5; E14, E15: producing at least one other metal layer (23; 33) of the timepiece component and/or carrying out an operation for machining a metal layer after separation of the substrate (10) on the upper and/or lower surface of the sheet.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: To provide a power-module substrate and a manufacturing method thereof in which small voids are reduced at a bonded part and separation can be prevented. Bonding a metal plate of aluminum or aluminum alloy to at least one surface of a ceramic substrate by brazing, when a cross section of the metal plate is observed by a scanning electron microscope in a field of 3000 magnifications in a depth extent of 5 ?m from a bonded interface between the metal plate and the ceramic substrate in a width area of 200 ?m from a side edge of the metal plate, residual-continuous oxide existing continuously by 2 ?m or more along the bonded interface has total length of 70% or less with respect to a length of the field.

Abstract: A power converter for a power system includes an input ceramic layer, an output ceramic layer, an input stage coupled to the input ceramic layer, an output stage coupled to the output ceramic layer, and a planar transformer coupled between said input stage and said output stage. The input receives a power input and the output stage generates a power output at least partially as a function of the power input. The planar transformer includes an input winding coupled to the input stage and an output winding coupled to the output stage. The input winding has a plurality of input turns and the output winding has a plurality of output turns. The input turns interleave the output turns.

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

Abstract: A wiring board includes a first electrically-conductive layer; and a first resin layer covering the first electrically-conductive layer, the first resin layer including a resin portion and inorganic insulating particles dispersed in the resin portion. The first resin layer has a first layer region which is in contact with one main surface and side surfaces of the first electrically-conductive layer, and a second layer region which is located on a side of the first layer region which side is opposite to the first electrically-conductive layer. The inorganic insulating particles include a plurality of first inorganic insulating particles contained in the first layer region, and a plurality of second inorganic insulating particles contained in the second layer region. A content rate of the first inorganic insulating particles in the first layer region is lower than a content rate of the second inorganic insulating particles in the second layer region.

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

Abstract: Methods for depositing a nanocrystalline diamond layer are disclosed herein. The method can include delivering a sputter gas to a substrate positioned in a processing region of a first process chamber, the first process chamber having a carbon-containing sputter target, delivering an energy pulse to the sputter gas to create a sputtering plasma, the sputtering plasma having a sputtering duration, the energy pulse having an average power between 1 W/cm2 and 10 W/cm2 and a pulse width which is less than 100 ?s and greater than 30 ?s, the sputtering plasma being controlled by a magnetic field, the magnetic field being less than 300. Gauss, and delivering the sputtering plasma to the sputter target to form an ionized species, the ionized species forming a crystalline carbon-containing layer on the substrate.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: A ceramic base body, which is a ceramic heater which suppresses noise radiation and thus has little adverse effect on surrounding electronic devices, includes a plurality of ceramic layers, and a mixed-material layer disposed between two ceramic layers, the mixed-material layer being formed of a mixture of a ceramic material and a metal material. Between the ceramic layer and the mixed-material layer, a heat-generating resistor which generates heat by a passage of electric current therethrough is disposed. Radiation of a high-frequency component generated by the passage of electric current through the heat-generating resistor is suppressed by the mixed-material layer, wherefore the adverse effect of the radiation on surrounding electronic devices can be reduced.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: A multi-layer wiring board includes wiring layers stacked on a substrate with an insulating layer between each layer. A wire formed in the wiring layer consists of a first layer and a second layer to form a double layered structure. The first layer is made of a first conductive material and the second layer is made of a second conductive material having relative magnetic permeability of 10 or more and larger than that of the first conductive material. The characteristic impedance of the wire is adjusted to a value closer to 50 ohms than that of a wire which has the same thickness as of the wire with the double layered structure, and is made only of the first conductive material.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: A substrate for a light-emitting diode comprising a metal base with a thickness of a predetermined value or more is constituted so that the thickness of a top conductor for an electrical connection with a light-emitting diode (LED) in a predetermined range falls within a predetermined range and the thickness of an insulation layer which electrically insulates the metal base and the top conductor and the thickness of the top conductor meet a predetermined relation. Thereby, a substrate for a light-emitting diode which can show a high heat dissipation capacity by achieving a low thermal resistance as the total thermal resistance of the whole substrate without reducing insulation reliability and high-humidity reliability of the substrate is provided.

Abstract: A substrate for a light-emitting diode comprising a metal base with a thickness of a predetermined value or more is constituted so that the thickness of a top conductor for an electrical connection with a light-emitting diode (LED) in a predetermined range falls within a predetermined range and the thickness of an insulation layer which electrically insulates the metal base and the top conductor and the thickness of the top conductor meet a predetermined relation. Thereby, a substrate for a light-emitting diode which can show a high heat dissipation capacity by achieving a low thermal resistance as the total thermal resistance of the whole substrate without reducing an insulation reliability and high-humidity reliability of the substrate is provided.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.

Abstract: A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: Various embodiments of a semiconductor chip device that include a circuit board and a stiffener frame and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a circuit board and coupling a stiffener frame to the circuit board. The stiffener frame includes a first opening that defines an interior wall. The interior wall includes a notch.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film.

Abstract: A photonic crystal is grown within a semiconductor structure, such as a III-nitride structure, which includes a light emitting region disposed between an n-type region and a p-type region. The photonic crystal may be multiple regions of semiconductor material separated by a material having a different refractive index than the semiconductor material. For example, the photonic crystal may be posts of semiconductor material grown in the structure and separated by air gaps or regions of masking material. Growing the photonic crystal, rather than etching a photonic crystal into an already-grown semiconductor layer, avoids damage caused by etching which may reduce efficiency, and provides uninterrupted, planar surfaces on which to form electric contacts.

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.

Abstract: A semiconductor device has a substrate. A first die is electrically attached to a first surface of the substrate. A shield spacer having a first and second surface is provided wherein the second surface of the shield spacer is attached to a first surface of the first die. A plurality of wirebonds are attached to the shield spacer and to the substrate. A mold compound is provided for encapsulating the first die, the shield spacer, and the wirebonds.

Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.