Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which are able to form a conductive film, which is dense, includes a low concentration of source-derived impurities and has low resistivity, at a higher film-forming rate. The substrate processing apparatus includes a processing chamber configured to stack and accommodate a plurality of substrates; a first processing gas supply system configured to supply a first processing gas into the processing chamber; a second processing gas supply system configured to supply a second processing gas into the processing chamber; and a control unit configured to control the first processing gas supply system and the second processing gas supply system.

Abstract: A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection.

Abstract: A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor is not provided in a package.

Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.

Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

Abstract: Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Abstract: Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

Abstract: A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.

Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

Abstract: An integrated circuit package system includes forming lead structures including a dummy tie bar having an intersection with an outer edge of the integrated circuit package system, and connecting an integrated circuit die to the lead structures.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product.

Abstract: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.

Abstract: An electrical characteristics test for a semiconductor integrated circuit using a Kelvin contact method can be conducted in a pre-process without obstructing the reduction in size of a semiconductor chip or without complicating the circuit design. A probe card in a testing apparatus includes probes for Kelvin contact, the probes for Kelvin contact including a coil probe and a POGO pin probe disposed inside the coil probe, and a probe for two-terminal measurement. Electrode pads formed in each chip area over a wafer are in a relation of A=B<2A, given that the area of one of the electrode pads with which the probe for Kelvin contact comes into contact is B and the area of the other electrode pad with which the probe for two-terminal measurement comes into contact is A.

Abstract: A semiconductor device includes a through electrode penetrating a semiconductor substrate, a conductor pad formed on the through electrode and made of a conductor electrically connected to the through electrode, and an interconnection layer formed on a surface of the semiconductor substrate and electrically connected to the conductor pad.

Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.

Abstract: A semiconductor package has a non-uniform contact arrangement in which clustered contacts (e.g., a group of ground contacts, a group of power contacts, and/or a group of heatslug contacts) are placed closer together than I/O contacts. In one embodiment, I/O contacts near a cluster have a pitch in at least one direction that is larger than other I/O contacts. A local increase in the pitch of I/O contacts may be used to increase the line width and/or spacing of traces that fan out from corresponding pads on a printed circuit board.

Abstract: For a DC to DC converter circuit integrated on a packaged die, the relative positions of various die pads and power MOSFETs on the die for a small outline integrated circuit package are described.

Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts.

Abstract: A substrate for an electronic circuit is provided wherein the substrate comprises a plurality of contact areas (304), a plurality of dielectric areas (307), and a conductor path (301), wherein each of the plurality of contact areas is surrounded by a respective one of the dielectric areas, and wherein at least two of the contact areas are connected with each other by the conductor path. Furthermore, the conductor path is formed at the dielectric area in such a way that it completely covers the dielectric area.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract: A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer.

Abstract: Provided is an adhesive tape which adheres two members to each other and decreases problems that may occur due to contraction and expansion of the adhered members when the temperature of the adhered two members changes. The adhesive tape includes: a base film having insulating properties; and an adhesive agent that adheres on both sides of the base film, wherein a coefficient of thermal expansion of the base film is 10 ppm or lower, a coefficient of thermal expansion of the adhesive tape is lower than 17 ppm, and an occupation rate of the base film in the adhesive tape exceeds 50%.

Abstract: A semiconductor component includes a substrate, at least one oblong first electrode disposed on the substrate and at least one second electrode disposed on the substrate. The first and/or the second electrode respectively are closed in its longitudinal direction.

Abstract: Provided is a semiconductor device that may prevent a test pad planned not to be wire bonded from being wire bonded. The semiconductor device may include a bonding pad planned to be wire bonded and a test pad planned not to be wire bonded, and a passivation layer including a first opening portion exposing part of the bonding pad and a second opening portion exposing part of the test pad, wherein the diameter of the first opening portion is greater than the diameter of a tip of a bonding wire, and the diameter of the second opening portion is less than the diameter of the tip of the bonding wire.

Abstract: A submount for a micro-component includes a semiconductor substrate having a cavity defined in a front-side of the substrate in which to mount the micro-component. The submount also includes a thin silicon membrane portion at a bottom of the cavity and thicker frame portions adjacent to sidewalls of the cavity. The substrate includes an electrically conductive feed-through connection extending from a back-side of the substrate at least partially through the thicker silicon frame portion. Electrical contact between the feed-through connection and a conductive layer on a surface of the cavity is made at least partially through a sidewall of the cavity.

Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

Abstract: A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one die. At least one topside interconnect layer is coupled to a top surface of the at least one die. One or more embedded electrical connections is configured to provide an electrical interconnection between the at least one bottomside interconnect layer and the at least one die and/or the at least bottomside interconnect layer and the at least one topside interconnect layer and/or the at least one topside interconnect layer and the at least one die, wherein the at least one bottomside interconnect layer includes one or more electrical contacts on a bottom surface of the multichip module and the at least topside interconnect layer includes one or more electrical contacts on a top surface of the multichip module.

Abstract: A power semiconductor module with segmented base plate. One embodiment provides a semiconductor module including a base plate and at least two circuit carriers. The base plate includes at least two base plate segments spaced distant from one another. Each of the circuit carriers includes a ceramic substrate provided with at least a first metallization layer. Each of the circuit carriers is arranged on exactly one of the base plate segments. At least two of the circuit carriers are spaced distant from one another.

Abstract: A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Abstract: An audio power amplifier package includes a non-signal lead, a first non-signal pad, a second non-signal pad and a plurality of bonding wires. The first non-signal pad and the second non-signal pad are disposed on a substrate. The bonding wires connect the non-signal lead to the first non-signal pad and the second non-signal pad respectively.

Abstract: The first external electrode has a main body portion a part of which is buried in a side wall of a case and joining portions protruding from an end of the main body portion toward the inside of the case. Each joining portion of the first external electrode is formed to have a thickness smaller than that of the main body portion, and an end portion of each joining portion is directly joined onto a wiring pattern of the insulating substrate through ultrasonic joining. Therefore, a load and ultrasonic vibration necessary for joining the joining portion onto the wiring pattern can be suppressed, which makes it possible to directly join the first external electrode onto the wiring pattern of the insulating substrate without damaging an insulating member of the insulating substrate.

Abstract: A micro USB memory package and method for manufacturing the same, which can meet the USB standard specification, can have a light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof. The micro USB memory package comprises a substrate with a plurality of circuit patterns formed on the top surface thereof, at least one of passive elements connected with the circuit patterns of the substrate, at least one of controllers connected with the circuit patterns of the substrate, at least one of flash memories connected with the circuit patterns of the substrate, and an encapsulation part encapsulating the passive elements, the controllers and the flash memories on the substrate, and at least one of USB lands connected with the circuit patterns by a conducting via are formed on the under surface of one side of the substrate.

Abstract: A method for forming a three-dimensional structure comprises: a first step of dropping a liquid material containing a structure-forming material and a solvent onto a structure forming surface; and a second step of drying at least a part of the solvent in the dropped liquid material to form a deposit layer on the structure forming surface, wherein the first step and the second step are repeated while a dropping position of the liquid material is shifted such that a next droplet of the liquid material is dropped onto the deposit layer formed of the previously-dropped liquid material to repeatedly accumulate the deposit layers on the structure forming surface, thereby forming a three-dimensional structure having at least one inclination portion inclined with respect to the structure forming surface.

Abstract: A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring.