Abstract: A power semiconductor device includes a semiconductor wafer having a junction and a junction termination laterally surrounding the junction. A protection layer covers the lateral side of the semiconductor wafer and covers the second main side at least in an area of the junction termination. A first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer. An interface between the first metal disk and the semiconductor wafer is a free floating interface. A metal layer sandwiched between the first metal disk and the semiconductor wafer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.

Abstract: A solder product 20 includes: a lead-free solder part 21 containing tin as a main component and a metal element other than lead as a secondary component; and a carboxylic acid having 10 to 20 carbons, the carboxylic acid being mainly distributed over the surface of the solder product 20 to form a surface layer 22. The carboxylic acid is preferably a fatty acid having 12 to 16 carbons, and more preferably a palmitic acid.

Abstract: A connection body for which a determination of the pass/fail of the electrical continuity can be made by an indentation inspection and in which conduction reliability is ensured.

Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).

Abstract: An electronic device includes a heat sink, a substrate mounted on the heat sink, a coating layer formed on the substrate, a lead frame fixed to the heat sink, and a mold resin sealing the substrate and the lead frame. The coating layer is made of one of a polyimide-based resin and a polyamideimide-based resin. The lead frame has a fixing terminal fixed to the heat sink through an adhesive layer. The adhesive layer is made of the same material as the coating layer.

Abstract: A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each site includes a die attach pad surrounded by terminal pads. The pads are formed of multiple materials including a lower layer and a body portion. An upper layer can also be provided over the body portion. A chip is mounted upon the die pad and wire bonds extend from the chip to the terminal pads. These parts are all encapsulated within a mold compound. The body portion is preferably formed by providing a matrix of metal powder and a suspension medium at locations where the pads are to be located. Heat is applied to disperse the suspension medium and sinter the metal powder to form the body portion. After encapsulation the temporary support member can be peeled away and the package sites isolated from each other.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A package structure is adapted for mounting at least one light emitting diode (LED) die. The package structure includes an insulating housing, and a lead frame unit including two spaced-apart conductive bodies. Each of the conductive bodies has opposite first and second conductive terminals spaced-apart from each other along an axial direction. The first conductive terminals extend into the insulating housing. The second conductive terminals are exposed outwardly of the insulating housing. Each of the conductive bodies further has two side edges spaced-apart from each other along a transverse direction perpendicular to the axial direction, and a concave-convex structure disposed at the side edges and surrounded by the insulating housing.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A semiconductor device includes a vertical power semiconductor chip including a semiconductor layer. A first terminal is at a first side of the semiconductor layer and a second terminal is at a second side of the semiconductor layer opposite the first side along a first direction. A drift zone is within the semiconductor layer between the first terminal and the second terminal. The drift zone has, in a central part, a compressive stress of at least 100 MPa along a second direction perpendicular to the first direction. The central part extends from 40% to 60% of an overall extension of the drift zone along the first direction and into a depth of the semiconductor layer of at least 10 ?m with respect to at least one of the first side and the second side of the semiconductor layer.

Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

Abstract: A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.

Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

Abstract: The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the invention, when producing a tin or a solder alloy used for electronic components, an ingot of a tin or a solder alloy is heated, melted and delivered to a reactor. Also, a solution containing organic acid having a carboxyl group (—COOH) is delivered to the reactor. After stirring and mixing the two liquids intensively, the mixed liquid is separated into a molten tin or a molten solder alloy liquid and an organic acid solution according to the difference in specific gravity. Then, the respective liquids are circulated to the reactor, and the metal oxides and the impurities existing in the molten tin or the molten solder alloy are removed, and the molten tin or the molten alloy is purified to have oxygen concentration of 5 ppm or less.

Abstract: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.

Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.

Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.

Abstract: An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the insulating layer, wherein ones of the plurality of conductive members contact the second surface of the electrode.

Abstract: A method of fabricating a semiconductor device includes forming a gate insulating film on an upper surface of a silicon substrate, forming a polycrystalline silicon film on the gate insulating film, and etching the polycrystalline silicon film, the gate insulating film, and the silicon substrate with a patterned coating type carbon film and a silicon nitride film so that first and second trenches are simultaneously formed. The first trench has a first width and a first depth and the second trench has a second width larger than the first width and the second depth larger than the first depth.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 ?m, which rewiring plate includes a base body and passages with carbon nanotubes, the lower end of the passages opening out into contact connection surfaces, and the carbon nanotubes forming an electrically conductive connection from the contact connection surfaces to the front surface of the base body.

Abstract: A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations to selectively determine the use of the wirebond pad under control of the microcontroller's processor. The microcontroller can be configured using configurable analog and configurable digital blocks to perform any of a plurality of functions with certain of the pinouts determined under program control.