Abstract: An LED module includes: a package having electrodes provided on the outer surface of opposing sidewalls, and a light-emitting element connected to the electrodes and mounted on the package; a base member having a copper metal; an insulating layer stacked on the surface of the base member and having an insulating material; and a conductive wiring pattern connected to the electrodes by soldering and formed on the surface of the insulating layer. The insulating layer has a through-hole formed by removing a part of the section where the package is positioned, and a heat dissipation unit formed by soldering between the back surface of the package and the base member, which face one another with the through-hole interposed therebetween.

Abstract: A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature.

Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region

Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.

Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate.

Abstract: A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane.

Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.

Abstract: A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit.

Abstract: Disclosed herein is a power module package including: a first heat dissipation plate including a first flow path, a second flow path, and a third flow path which are sequentially formed, the first flow path and the third flow path being formed to have a step therebetween; and a second heat dissipation plate formed under the first heat dissipation plate, having one face and the other face, having a semiconductor device mounting groove formed in the one face thereof, and including a fourth flow path having one end connected to the second flow path and the other end connected to the third flow path, wherein a cooling material introduced through the first flow path is distributed to the third flow path and the fourth flow path based on the second flow path.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink.

Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.

Abstract: A composite structure 10 of a resin-diamagnetic material, including a diamagnetic material layer 12 and a resin layer 14 is obtained by a method including disposing particles of a diamagnetic material 22 and a resin 24 in a mold 30, applying a magnetic field to the diamagnetic material 22 disposed in the mold 30, and moving the diamagnetic material 22 in a direction away from at least a part of an inner surface of the mold 30, and then curing the resin 24 in the mold 30 thereby to produce a resin-diamagnetic material composite structure.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation.

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract: In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.

Abstract: A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.

Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.

Abstract: A packaged semiconductor device, comprising a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: A device has a passive cooling device having a surface, at least one active cooling device on the surface of the passive cooling device, and a thermal switch coupled to the passive cooling device, the switch having a first position that connects the active cooling device to a path of high thermal conductivity and a second position that connects the passive cooling device to the path of high thermal conductivity.

Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Abstract: The invention discloses a package structure with at least one portion of a first conductive element disposed in a through-opening of a first substrate. A conductive structure is disposed on the first substrate and the first conductive element, wherein the conductive structure is electrically connected to the first substrate and said at least one first I/O terminal of the first conductive element. The conductive structure comprises at least one of a second conductive element, a second substrate or a conductive pattern.

Abstract: A thermal interface material comprises an epoxy resin derived from nutshell oil or an epoxidized dimer fatty acid, or both, and fusible metal particles substantially devoid of added lead. Optionally, the TIM comprises a catalyst for the epoxy functionality.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface; a stacked structure on which the semiconductor chip is disposed; and a cooling body on which the stacked structure is disposed. The stacked structure includes a first thermal conductor fixed to the cooling body, an insulator disposed on the first thermal conductor, and a second thermal conductor disposed on the insulator and having the semiconductor chip disposed thereon. The first main surface of the semiconductor chip opposite to the second main surface in contact with the stacked structure is sealed with an insulation material. At least a part of the first thermal conductor protrudes outwardly of the insulation material in plan view.

Abstract: There is disclosed an integrated circuit (IC) package or semiconductor package including integrated spark or arc gaps which are uniquely configured to reduce the susceptibility of the package to being damaged from an electrostatic discharge (ESD) event. In an exemplary embodiment, each arc gap is collectively defined by an arc gap extension integrally connected to and protruding from the die pad of the package, and a corresponding lead thereof.

Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

Abstract: Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material.

Abstract: A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

Abstract: The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract: An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.