Selection Of Materials, Or Shaping, To Facilitate Cooling Or Heating, E.g., Heat Sinks (epo) Patents (Class 257/E23.101)
  • Patent number: 8610263
    Abstract: A P-side package unit and a N-side package unit are arranged on a main surface of a metal heatsink such that a main surface extends in a direction perpendicular to the main surface of the heatsink. Each of the P-side package unit and the N-side package unit is fixed by an end edge portion of a heatsink being clipped by a rail-shaped unit mounting part provided on the main surface of the heatsink.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunari Hino, Kiyoshi Arai
  • Patent number: 8609506
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8604619
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8598616
    Abstract: Disclosed are a light emitting device and a light unit using the same. The light emitting device includes a body, a light emitting diode installed in the body, a plurality of lead frames disposed in the body and electrically connected to the light emitting diode; and a heat dissipation member received in the body, thermally connected to the light emitting diode, and having a plurality of heat dissipation fins exposed from a lower surface of the body.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 3, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Gun Kyo Lee
  • Patent number: 8592974
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: November 26, 2013
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Patent number: 8586857
    Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Miasole
    Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
  • Patent number: 8587105
    Abstract: A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Nakao, Hiroshi Fukuyoshi
  • Publication number: 20130299960
    Abstract: A chip package having a lead frame and a molded portion. The lead frame includes a thermal pad and at least one electrode. The molded portion partially encapsulates the at least one electrode such that it is exposed on a top surface but not on a bottom surface. A bottom surface of the thermal pad is exposed for direct securement to an external heat sink. The molded portion is disposed between the at least one electrode and the heat sink to prevent a short circuit.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Inventor: Hsun-Wei Chan
  • Publication number: 20130285233
    Abstract: At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell
  • Patent number: 8564121
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 22, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Patent number: 8564120
    Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 22, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Anthony Mowry, David Farber, Fred Hause, Markus Lenski
  • Publication number: 20130270689
    Abstract: Provided are a semiconductor package capable of packaging and modularizing power semiconductor devices which are difficult to integrate due to heat generation, a semiconductor package module using the same, and a mounting structure thereof. The semiconductor package includes: a common connection terminal formed to have a flat plate shape; first and second electronic devices respectively bonded to both surfaces of the common connection terminals; first and second connection terminals having a flat plate shape and bonded to the first electronic device; and a third connection terminal having a flat plate shape and bonded to the second electronic device.
    Type: Application
    Filed: July 16, 2012
    Publication date: October 17, 2013
    Inventors: Kwang Soo KIM, Young Ki LEE, Bum Seok SUH, Kee Ju UM, Suk Ho LEE, Young Hoon KWAK
  • Patent number: 8558361
    Abstract: A power semiconductor module comprises: a heat dissipation plate; an insulating wiring board having an upper electrode and a lower electrode, the lower electrode joined to the heat dissipation plate via a first solder; a semiconductor chip joined to the upper electrode via a second solder; a first low-k dielectric film coating sides of the lower electrode and the first solder; a second low-k dielectric film coating sides of the semiconductor chip and the second solder; a case on the heat dissipation plate and surrounding the insulating wiring board and the semiconductor chip; and an insulator filled in the case and coating the insulating wiring board, the semiconductor chip, and the first and second low-k dielectric films.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: October 15, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuto Kawaguchi
  • Patent number: 8558373
    Abstract: According to one embodiment, a heatsink includes a base and heat radiation fins placed on one of surfaces of the base and arranged in parallel to each other with a submillimeter narrow pitch. Each of the multiple heat radiation fins has a submillimeter thickness, a length in a width direction of 60 mm or smaller, and a height of 40 mm or smaller. The heatsink assembly may be constituted by allaying a plurality of the heatsinks and thermally connecting each of the heatsinks to each other using a heat transport device.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kodani, Makoto Takeda
  • Patent number: 8557721
    Abstract: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Mattson Technology, Inc.
    Inventor: Paul J. Timans
  • Patent number: 8536687
    Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiyuki Hata
  • Patent number: 8535959
    Abstract: The present invention relates to a method for manufacturing large lighting which uses a power LED, such as for large LED lighting for street lamps, which incorporates a heat dissipation device that has the ability to dissipate heat with natural convection to maintain ambient temperature. The disclosed method is novel applied technology for producing a large LED lighting, such as for street lamps, which has a power LED device with a unique, rear heat dissipation capability. In addition to maximum thermal efficiency by heat dissipation, the present LED lighting system also increases luminous efficiency by providing high light emission with only a small quantity of LED power.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 17, 2013
    Inventor: Young Seob Lee
  • Patent number: 8531019
    Abstract: A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: September 10, 2013
    Assignee: Spansion LLC
    Inventor: Masanori Onodera
  • Publication number: 20130221514
    Abstract: Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device 1 comprising: a mounting substrate 70; a semiconductor chip 10 disposed on the mounting substrate 70 and a semiconductor substrate 26, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate 26, and a drain pad electrode 36 disposed on a back side surface of the semiconductor substrate 26 to be contacted with the mounting substrate 70; and a source connector SC disposed on the source pad electrode SP. The mounting substrate 70 and the drain pad electrode 36 are bonded by using solid phase diffusion bonding.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 29, 2013
    Applicants: ROHM CO., LTD., ARKANSAS POWER ELECTRONICS INTERNATIONAL, INC.
    Inventors: Takukazu OTSUKA, Bryon WESTERN, Brandon PASSMORE, Zach COLE
  • Patent number: 8518749
    Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 27, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Frederick R. Dahilig, Zigmund R. Camacho, Lionel Chien Hui Tay, Dioscoro A. Merilo
  • Patent number: 8519532
    Abstract: A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventors: Andreas Lenniger, Andre Uhlemann, Olaf Hohlfeld
  • Patent number: 8513816
    Abstract: The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on the back surface of a semiconductor element to be flip chip-connected onto an adherend, the film containing a resin and a thermoconductive filler, in which the content of the thermoconductive filler is at least 50% by volume of the film, and the thermoconductive filler has an average particle size relative to the thickness of the film of at most 30% and has a maximum particle size relative to the thickness of the film of at most 80%.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 20, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai
  • Patent number: 8513796
    Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: August 20, 2013
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Yu-Shan Hu
  • Patent number: 8508056
    Abstract: A heat releasing semiconductor package, a method for manufacturing the same, and a display apparatus including the same. The heat releasing semiconductor package includes a film, an electrode pattern formed over the film, a semiconductor device mounted over the electrode pattern, and a first heat releasing layer formed over the semiconductor device including the electrode pattern, the first heat releasing layer including a first adhesive and a first heat releasing material.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: August 13, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Sung-Jin Kim, Jun-Il Kim
  • Patent number: 8492911
    Abstract: An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: July 23, 2013
    Assignee: LSI Corporation
    Inventors: Mark A. Bachman, John W. Osenbach, Sailesh M. Merchant
  • Patent number: 8476656
    Abstract: A light-emitting diode includes a circuit board, a pair of electrodes provided on the circuit board, at least one light-emitting diode element electrically connected to the pair of electrodes, a central electrode for heat-dissipation, provided between the pair of electrodes on the circuit board, and a heat-dissipation plate disposed on the central electrode for heat-dissipation and including a reflection surface. The central electrode for heat-dissipation includes an upper central electrode disposed on the upper surface of the circuit board and a lower central electrode disposed on the lower surface of the circuit board and the upper central electrode thermally connected to the lower central electrode.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: July 2, 2013
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Norikazu Kadotani
  • Patent number: 8476116
    Abstract: A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Chen-Hua Yu
  • Publication number: 20130154079
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Oh Han Kim, Haengcheol Choi, KyungOe Kim
  • Publication number: 20130154080
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154078
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: DaeSik Choi, JoungIn Yang, MinJung Kim, KyungEun Kim
  • Publication number: 20130147026
    Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: ATI Technologies ULC
    Inventors: Roden R. TOPACIO, Liane Martinez, Yip Seng Low
  • Patent number: 8455931
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: June 4, 2013
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Publication number: 20130134574
    Abstract: A semiconductor device includes a semiconductor element placed over a substrate, a heat conducting material placed over the semiconductor element, and a radiator placed over the heat conducting material. The radiator has a plurality of projections which are arranged outside a region opposite to the semiconductor element and which protrude toward the substrate. Even if the heat conducting material flows out from over the semiconductor element at fabrication time, the heat conducting material which flows out is made by the plurality of projections to adhere to and spread along the radiator. As a result, the outflow or scattering of the heat conducting material toward the substrate or an electric trouble caused by it is prevented.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 30, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: FUJITSU SEMICONDUCTOR LIMITED
  • Patent number: 8450845
    Abstract: The object of the present invention is to efficiently dissipate heat from the upper and lower main surfaces of a semiconductor device carrying a semiconductor element. A semiconductor device (1) is provided with an insulating substrate (10A), an insulating substrate (10B) provided so as to face the insulating substrate (10A), and a semiconductor element (20) disposed between the insulating substrate (10A) and the insulating substrate (10B) and having a collector electrode and an emitter electrode provided on the side opposite to that of the collector electrode. The collector electrode is electrically connected to a metal foil (10ac) provided on the insulating substrate (10A), and the emitter electrode is electrically connected to the metal foil (10bc) provided on the insulating substrate (10B). As a result, heat generated by the semiconductor element (20) is efficiently dissipated from the upper and lower main surfaces of the semiconductor device (1).
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: May 28, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yoshinari Ikeda, Shin Soyano, Akira Morozumi, Kenji Suzuki, Yoshikazu Takahashi
  • Patent number: 8441128
    Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventor: Daniel Domes
  • Patent number: 8426980
    Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 23, 2013
    Assignee: National Chiao Tung University
    Inventors: Chau-Chin Su, Ying-Chieh Ho, Po-Hsiang Huang
  • Patent number: 8421217
    Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jon A. Casey, John S. Corbin, Jr., David Danovitch, Isabelle Depatie, Virendra R. Jadhav, Roger A. Liptak, Kenneth C. Marston, Jennifer V. Muncy, Sylvain Ouimet, Eric Salvas
  • Publication number: 20130087905
    Abstract: A curable organopolysiloxane composition in grease or paste form, which including: (A) an organopolysiloxane having at least two alkenyl groups bonded to silicon atom in one molecule; (B) an organohydrogenpolysiloxane having at least two hydrogen atoms bonded to silicone atom in the molecule; (C) gallium and/or a gallium alloy having a melting point of 0 to 70° C.; (D) a thermally conductive filler having an average particle size of 0.1 to 100 ?m; (E) a platinum-based catalyst; and (F) a polysiloxane of the following general formula (1): wherein R1 may be the same or different and represents a monovalent hydrocarbon group, R2 represents an alkyl group, an alkoxyl group, an alkenyl group or an acyl group, a is an integer of 5 to 100, and b is an integer of 1 to 3.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 11, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: SHIN-ETSU CHEMICAL CO., LTD.
  • Patent number: 8415786
    Abstract: A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 9, 2013
    Assignee: STATS ChipPac Ltd.
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Publication number: 20130082407
    Abstract: A method of making integrated circuit package assemblies including encapsulating a plurality of dies in an encapsulation layer having an exterior surface and attaching a heat sink strip to the exterior surface of the encapsulation layer. An integrated circuit package assembly and an intermediate product used in making an integrated circuit package assembly are also disclosed.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Donald C. Abbott, Margaret Rose Simmons-Matthews
  • Patent number: 8409930
    Abstract: A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: April 2, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Makoto Terui, Yasushi Shiraishi
  • Patent number: 8405194
    Abstract: A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 26, 2013
    Assignee: Denso Corporation
    Inventors: Masayoshi Nishihata, Yasushi Ookura
  • Patent number: 8399985
    Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 19, 2013
    Assignee: United Test And Assembly Center Ltd.
    Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
  • Patent number: 8395254
    Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 12, 2013
    Assignee: STATS Chippac Ltd.
    Inventors: Emmanuel Espiritu, Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Rachel Layda Abinan, Allan Ilagan
  • Publication number: 20130056871
    Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
  • Publication number: 20130056862
    Abstract: A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: OhHan Kim, WonJun Ko, DaeSik Choi
  • Patent number: 8391011
    Abstract: A cooling device includes a heat sink having a top plate, a bottom plate spaced from the top plate and fins between the top and bottom plates, a first metal member laminated to the side of the top plate that is opposite from the fins, and a first insulator laminated to the first metal member. The top plate, the bottom plate and the first metal member are each made of a clad metal that is composed of a base metal and a brazing metal, so that the fins are brazed to the top and bottom plates, the first metal member is brazed to the top plate, and the first insulator is brazed to the first metal member.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono
  • Publication number: 20130032935
    Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin M. O'Connell, Arvind K. Sinha, Kory W. Weckman
  • Patent number: 8368208
    Abstract: In some embodiments, a semiconductor cooling apparatus includes a monolithic array of cooling elements. Each cooling element of the monolithic array of cooling elements is configured to thermally couple to a respective semiconductor element of an array of semiconductor elements. At least two of the semiconductor elements have a different height and each cooling element independently flexes to conform to the height of the respective semiconductor element.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: February 5, 2013
    Assignee: Raytheon Company
    Inventors: Scott T. Johnson, Shadi S. Merhi
  • Patent number: 8367469
    Abstract: A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: February 5, 2013
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth