Selection Of Materials, Or Shaping, To Facilitate Cooling Or Heating, E.g., Heat Sinks (epo) Patents (Class 257/E23.101)
  • Patent number: 8350378
    Abstract: A diode, e.g., a press-fit power diode for a rectifier in a motor vehicle, includes a semiconductor chip which is connected to a head wire and a base via solder layers. A plastic sheathing, which is situated at least in the chip area and includes a plastic sleeve, enables a hard casting compound to be used and establishes a mechanical connection between the base and the head wire and forms a housing together with the base. An undercut, which extends into the casting compound, and a gap between the sleeve and the edge of the base achieve a compact design. Bevels provided on both sides enable the diode to be pressed into the rectifier from two sides.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: January 8, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Karin Hamsen, Jochen Dietrich
  • Patent number: 8338943
    Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 25, 2012
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventor: Kum Weng Loo
  • Publication number: 20120319266
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Patent number: 8330269
    Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Matthias Stecher, Tobias Smorodin
  • Publication number: 20120306067
    Abstract: According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Haw Tsao, Kuo-Chin Chang, Han-Ping Pu
  • Patent number: 8324723
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump that includes first, second and third bent corners that shape a cavity. The conductive trace includes a pad and a terminal. The semiconductor device is located within the cavity, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends into an opening in the adhesive and provides a recessed die paddle and a reflector for the semiconductor device. The conductive trace provides signal routing between the pad and the terminal.
    Type: Grant
    Filed: November 20, 2010
    Date of Patent: December 4, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8324720
    Abstract: A power semiconductor module assembly is disclosed including a power semiconductor module comprising a load terminal electrically conductively joined to a contact conductor. Part of the heat materializing during operation of the power semiconductor module in the load terminal is dissipated by using a heat dissipating element.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Infineon Technologies AG
    Inventor: Martin Schulz
  • Patent number: 8318546
    Abstract: Thermal management is provided for a device. The device may include a substrate having a mounting area on a first surface of the substrate. The device may also include first thermal vias extending from the mounting area to at least an interior of the substrate. The device may also include at least one thermal plane substantially parallel to the first surface of the substrate, the at least one thermal plane being in thermal contact with at least one of the first thermal vias. The device may also include a heat sink attachment area, and second thermal vias extending from the heat sink attachment area to the interior of the substrate, the at least one thermal plane being in thermal contact with the second thermal vias.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: November 27, 2012
    Assignee: Juniper Networks, Inc.
    Inventor: David J. Lima
  • Patent number: 8319324
    Abstract: Provided are a high I/O semiconductor chip package in which a processor and a memory device are connected to each other via through electrodes and a method of manufacturing the high I/O semiconductor chip package. The high I/O semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, each memory device being arranged in a matrix in chip regions partitioned by a scribe region; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of through electrodes arranged along peripheral portions of the memory devices and connecting the first and second semiconductor chips to the second circuit patterns of the substrate.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Joo Lee
  • Patent number: 8314483
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8310045
    Abstract: A semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface, a heat dissipation member, defined with a cavity, disposed on the first surface of the first semiconductor chip and having a plurality of metal pillars which contact the first semiconductor chip, and one or more second semiconductor chips stacked on the first surface of the first semiconductor chip in the cavity to be electrically connected with one another and with the first semiconductor chip.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 13, 2012
    Assignee: SK Hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 8310067
    Abstract: A package is provided. The package includes a substrate having first and second surfaces, a stiffener coupled to the first surface of the substrate, and a thermal connector coupled to the second surface of the substrate that is configured to be coupled to a printed circuit board.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 13, 2012
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Reza-ur Rahman Khan
  • Patent number: 8304897
    Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Siva Prakash Gurrum, Paul J Hundt, Vikas Gupta
  • Patent number: 8304279
    Abstract: An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected to patterned electrodes. The package also includes an anodized insulation layer formed between the patterned electrodes and the substrate and a lens covering over the light source of the substrate. The Al substrate provides superior heat radiation effect of the LED, thereby significantly increasing the lifetime and light emission efficiency of the LED.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Ki Lee, Seog Moon Choi, Sang Hyun Shin
  • Patent number: 8299605
    Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S Basker, Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, Charles W Koburger, III, Krishna V Singh
  • Patent number: 8299608
    Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, David R. Motschman, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jiantao Zheng
  • Publication number: 20120261811
    Abstract: A semiconductor device includes an insulating substrate, a metal pattern formed on the insulating substrate, a power terminal bonded onto the metal pattern, and a plurality of power chips bonded onto the metal pattern. The plurality of power chips are all separated from the power terminal by a distance sufficient to thermally isolate the plurality of power chips from the power terminal.
    Type: Application
    Filed: December 2, 2011
    Publication date: October 18, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hidetoshi NAKANISHI, Yuji Miyazaki
  • Publication number: 20120248596
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Application
    Filed: June 8, 2012
    Publication date: October 4, 2012
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20120248595
    Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.
    Type: Application
    Filed: June 8, 2012
    Publication date: October 4, 2012
    Applicant: MonolithlC 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
  • Patent number: 8278677
    Abstract: Disclosed is a light emitting diode lamp that has low resistance to heat emitted therefrom. The LED lamp may include a heat coupling member thermally coupling a top part of a first lead to a top part of a second lead. The LED lamp may further include one or more top parts for lowering thermal resistance of the LED lamp. This configuration facilitates heat transfer from the first lead having an LED chip mounted thereon to the top part of the second lead and/or to the other top parts, lowering resistance to heat emitted from the LED lamp.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 2, 2012
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Zhbanov Alexander
  • Patent number: 8278742
    Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Rajeev D. Joshi
  • Publication number: 20120241939
    Abstract: A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.
    Type: Application
    Filed: June 8, 2012
    Publication date: September 27, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Byung Tai Do, Zigmund R. Camacho
  • Publication number: 20120241940
    Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Application
    Filed: June 8, 2012
    Publication date: September 27, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 8273610
    Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 25, 2012
    Assignee: MonolithIC 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
  • Publication number: 20120235292
    Abstract: In one embodiment, there is provided a heat radiating component. The heat radiating component includes: a base material made mainly of copper; an electroplated aluminum layer that covers at least a part of a surface of the base material; and an alumite layer formed on the electroplated aluminum layer and formed by anodic-oxidizing the electroplated aluminum layer.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 20, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yoriyuki Suwa, Kenji Kawamura
  • Patent number: 8269340
    Abstract: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Maurice McGlashan-Powell, Soojae Park, Edward Yarmchuk
  • Patent number: 8269339
    Abstract: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventor: Keiji Matsumoto
  • Patent number: 8269248
    Abstract: Apparatus may be provided including a high power light emitting diode (LED) unit, at least one printed circuit board, and an interfacing portion of a heat sink structure. The high power LED unit includes at least one LED die, at least one first lead and at least one second lead, and a heat sink interface. The at least one printed circuit board includes a conductive pattern configured to connect both the at least one first lead and the at least one second lead to a current source. The interfacing portion of the heat sink structure is that portion through which a majority of heat of the heat sink interface is transmitted. The interfacing portion is directly in touching contact with a majority of a heat transfer area of the heat sink interface.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: September 18, 2012
    Inventor: Joseph B. Thompson
  • Publication number: 20120217630
    Abstract: According to one embodiment, a heatsink includes a base and heat radiation fins placed on one of surfaces of the base and arranged in parallel to each other with a submillimeter narrow pitch. Each of the multiple heat radiation fins has a submillimeter thickness, a length in a width direction of 60 mm or smaller, and a height of 40 mm or smaller. The heatsink assembly may be constituted by allaying a plurality of the heatsinks and thermally connecting each of the heatsinks to each other using a heat transport device.
    Type: Application
    Filed: May 8, 2012
    Publication date: August 30, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya KODANI, Makoto TAKEDA
  • Patent number: 8241964
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: August 14, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8236617
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8232634
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: 8227912
    Abstract: As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer.
    Type: Grant
    Filed: October 10, 2004
    Date of Patent: July 24, 2012
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akihiro Morimoto
  • Patent number: 8222728
    Abstract: An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: July 17, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Kuang Yu, Chun-Kai Liu, Ming-Ji Dai, Chih-Yuan Cheng
  • Patent number: 8222731
    Abstract: In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate having conductive traces and pad landings. The conductive traces have pad landings. An IC is mounted on the substrate. The IC has bonding pads. With conductive wires, the IC bonding pads are connected to the pad landings, which in turn, are connected to the conductive traces. A heat slug, having predetermined height, is disposed on the substrate surface. The heat slug includes a plurality of mounting feet providing mechanical attachment to the substrate. A cavity in the heat slug accommodates the IC. A plurality of first-size openings surrounds the IC. A second-size opening constructed from one of the first size-openings, is larger than the first-size opening. The second size-opening facilitates the introduction of molding compounds into the cavity of the heat slug.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: July 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Chen, Kuo-Wen Peng, Ker-Chang Hsieh
  • Patent number: 8222729
    Abstract: An electric power converter includes: a heat sink having a heat receiving surface; a semiconductor module including a metal plate having a heat radiation surface, a switching element on the metal plate opposite to the heat radiation surface, and a resin member covering a part of the metal plate and the switching element; a heat radiation member between the heat receiving surface and the semiconductor module for transmitting heat of the switching element to the heat receiving surface via the metal plate. The heat receiving surface includes a concavity, and the heat radiation surface includes a convexity. The heat radiation member has a predetermined area sandwiched between the concavity and the convexity.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: July 17, 2012
    Assignee: Denso Corporation
    Inventor: Syuhei Miyachi
  • Publication number: 20120175765
    Abstract: A semiconductor device is disclosed that includes an insulation substrate, a metal wiring layer, a semiconductor element, a heat sink, and a stress relaxation member located between the insulation substrate and the heat sink. The heat sink has a plurality of partitioning walls that extend in one direction and are arranged at intervals. The stress relaxation member includes a stress absorbing portion formed by through holes extending through the entire thickness of the stress relaxation member. Each hole is formed such that its dimension along the longitudinal direction of the partitioning walls is greater than its dimension along the arranging direction of the partitioning walls.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Applicants: SHOWA DENKO K.K., KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Shogo MORI, Shinobu TAMURA, Shinobu YAMAUCHI, Taizo KURIBAYASHI
  • Publication number: 20120175762
    Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshiyuki HATA
  • Publication number: 20120168931
    Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III, Krishna V. Singh
  • Publication number: 20120168916
    Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 8212353
    Abstract: Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Altera Corporation
    Inventors: Wen-chou Vincent Wang, Yuan Li, Bruce Euzent, Vadali Mahadev
  • Patent number: 8207598
    Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 26, 2012
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow, Sheila Marie L. Alvarez
  • Publication number: 20120153454
    Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.
    Type: Application
    Filed: May 9, 2011
    Publication date: June 21, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Kai Liu, John H. Lau, Ming-Ji Dai, Ra-Min Tain
  • Patent number: 8203200
    Abstract: A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: June 19, 2012
    Assignee: Miasole
    Inventors: Whitfield G. Halstead, Steven Croft, Shawn Everson
  • Patent number: 8202765
    Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: June 19, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jon A. Casey, John S. Corbin, Jr., David Danovitch, Isabelle Depatie, Virendra R. Jadhav, Roger A. Liptak, Kenneth C. Marston, Jennifer V. Muncy, Sylvain Ouimet, Eric Salvas
  • Publication number: 20120139076
    Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 7, 2012
    Applicant: STMicroelectronics Pte. Ltd.
    Inventors: Ravi Shankar, Olivier Le Neel
  • Publication number: 20120139096
    Abstract: A semiconductor module including a cooling unit by which a fine cooling effect is obtained is provided. A plurality of cooling flow paths (21c) which communicate with both of a refrigerant introduction flow path which extends from a refrigerant introduction inlet and a refrigerant discharge flow path which extends to a refrigerant discharge outlet are arranged in parallel with one another in a cooling unit (20). Fins (22) are arranged in each cooling flow path (21c). Semiconductor elements (32) and (33) are arranged over the cooling unit (20) so that the semiconductor elements (32) and (33) are thermally connected to the fins (22). By doing so, a semiconductor module (10) is formed. Heat generated by the semiconductor elements (32) and (33) is conducted to the fins (22) arranged in each cooling flow path (21c) and is removed by a refrigerant which flows along each cooling flow path (21c).
    Type: Application
    Filed: July 28, 2010
    Publication date: June 7, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Akira Morozumi, Keiichi Higuchi
  • Publication number: 20120139098
    Abstract: Disclosed herein is a power package module, including: a power package mounted with a plurality of semiconductor chips; a heat radiation module coming into contact with the power package and including a first heat radiation member for discharging heat generated from the power package; and a second heat radiation member, one side of which is connected to the first heat radiation member and the other side of which is connected to the power package.
    Type: Application
    Filed: January 19, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kwan Ho LEE, Seog Moon CHOI
  • Patent number: 8193633
    Abstract: Provided is a heat conductive sheet obtained by dispersing an inorganic filler in a thermosetting resin, in which the inorganic filler contains secondary aggregation particles formed by isotropically aggregating scaly boron nitride primary particles having an average length of 15 ?m or less, and the inorganic filler contains more than 20 vol % of the secondary aggregation particles each having a particle diameter of 50 ?m or more. The heat conductive sheet is advantageous in terms of productivity and cost and excellent in heat conductivity and electrical insulating properties.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 5, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Mimura, Hideki Takigawa, Hiroki Shiota, Kazuhiro Tada, Takashi Nishimura, Hiromi Ito, Seiki Hiramatsu, Atsuko Fujino, Kei Yamamoto, Motoki Masaki
  • Patent number: 8193634
    Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 5, 2012
    Inventors: Andre Wong, Sukbhir Bajwa