Abstract: A ceramic electronic device includes: a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the multilayer chip, the first end face facing with the second end face; a first external electrode provided on the first end face; and a second external electrode provided on the second end face, wherein a silane film is provided on a surface of the ceramic electronic device, and wherein an organic compound is provided on the silane film, and has a siloxane bonding.

Abstract: A multilayer ceramic electronic component includes a multilayer body including layered ceramic layers and having a rectangular parallelepiped shape, and first and second outer electrodes covering both end surfaces of the multilayer body and extending from both the end surfaces so as to cover at least portions of a first main surface, a second main surface, a first side surface, and a second side surface of the multilayer body. An insulating layer is provided on a surface of the first main surface of the multilayer body. The first outer electrode and the second outer electrode disposed on the first main surface side are disposed on the insulating layer.

Abstract: An integrated circuit package structure and a package method. The integrated circuit package structure includes: a semiconductor chip, an encapsulation layer covering the semiconductor chip, the encapsulation layer including a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3; wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.

Abstract: A pre-ceramic support structure for additive manufacturing, that upon thermal processing, is soluble in various solvents.

Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.

Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

Abstract: A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

Abstract: An object of the present invention is to enhance the reliability of an MEMS sensor formed on a semiconductor integrated circuit device. To achieve this object, a semiconductor device of the present invention comprises: a semiconductor integrated circuit device; a lower passivation film of silicon nitride, etc. . . . formed on the semiconductor integrated circuit device and having high moisture resistance and high chemical resistance; a MEMS portion formed on the lower passivation film and including a cavity 12; and an upper passivation film 11 formed on the top surface of the MEMS portion such that the MEMS portion is hermetically sealed by the upper and lower passivation films.

Abstract: Disclosed are an SiC semiconductor element and manufacturing method for an SiC semiconductor element in which the interface state density of the interface of the insulating film and the SiC is reduced, and channel mobility is improved. Phosphorus (30) is added to an insulating film (20) formed on an SiC semiconductor (10) substrate in a semiconductor element. The addition of phosphorous to the insulating film makes it possible to significantly reduce the defects (interface state density) in the interface (21) of the insulating film and the SiC, and to dramatically improve the channel mobility when compared with conventional SiC semiconductor elements. The addition of phosphorus to the insulating film is carried out by heat treatment. The use of heat treatment to add phosphorous to the insulating film makes it possible to maintain the reliability of the insulating film, and to avoid variation in channel mobility and threshold voltage.

Abstract: Power amplifiers and methods of coating a protective film of alumina (Al2O3) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Abstract: A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like.

Abstract: A semiconductor die is attached to a substrate by a glass frit layer. Gas that might be trapped between the die and the glass frit layer during firing of the glass frit can escape through passages that are formed against the bottom surface of the die by topographies that extend away from and which are substantially orthogonal to the bottom of the die.

Abstract: This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Abstract: Power amplifiers and methods of coating a protective film of alumina (Al2O3) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Abstract: The present invention provides a multiple layer that comprises two or more first inorganic material layers; and one or more second inorganic material layers that are positioned between the two first inorganic material layers and have the thickness of less than 5 nm, in which the first inorganic material layer is formed of one or more materials that are selected from silicon oxides, silicon carbide, silicon nitride, aluminum nitride and ITO, and the second inorganic material layer is formed of one or more materials that are selected from magnesium, calcium, aluminum, gallium, indium, zinc, tin, barium, and oxides and fluorides thereof, a multiple film that comprises the multiple layer, and an electronic device that comprises the multiple film.

Abstract: A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Abstract: A ceramic electronic component has a chip element body having a conductor arranged inside, external electrodes, and a discrimination layer. The chip element body has first and second end faces facing each other, first and second side faces being perpendicular to the first and second end faces and facing each other, and third and fourth side faces being perpendicular to the first and second end faces and to the first and second side faces and facing each other. The external electrodes are formed on the first and second end faces, respectively, of the chip element body. The discrimination layer is provided on at least one side face out of the first side face and the second side face in the chip element body. The chip element body is comprised of a first ceramic. The discrimination layer is comprised of a second ceramic different from the first ceramic and has a color different from that of the third and fourth side faces.

Abstract: A solid element device includes a solid element, an electric power receiving and supplying part for receiving electric power from and supplying the electric power to the solid element, and an inorganic sealing material for sealing the solid element. The inorganic sealing material includes a low melting glass selected from SiO2—Nb2O5-based, B2O3—F-based, P2O5—F-based, P2O5—ZnO-based, SiO2—B2O3—La2O3-based, and SiO2—B2O3-based low melting glasses.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: A solid state device has a solid state component, a power receiving/supplying portion that mounts the solid state component thereon for receiving/supplying electrical power from/to the solid state component, and a glass sealing portion that seals the solid state component. The glass sealing portion is formed of a B2O3—SiO2—Li2O—Na2O—ZnO—Nb2O5 based glass, which is composed of 21 wt % to 23 wt % of B2O3, 11 wt % to 13 wt % of SiO2, 1 wt % to 1.5 wt % of Li2O, and 2 wt % to 2.5 wt % of Na2O.

Abstract: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip, a second metal layer attached the second face of the semiconductor chip, and electrically conducting material configured to connect the first metal layer with the second metal layer.

Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Abstract: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip, a second metal layer attached the second face of the semiconductor chip, and electrically conducting material configured to connect the first metal layer with the second metal layer.

Abstract: At least one film composite is laminated on a surface of at least one electrical component. The film composite includes at least one electrically-conducting plastic film with at least one electrically conducting conductor. The electrically-conducting plastic film has a high-ohmic resistance. This method may be used in planar large-surface electrical contacting technology for the production of modules with power semiconductors, where an electrical contacting of the components is achieved by the plastic films. A low lateral electrical conductivity is achieved, such that an electrical charging of the plastic films required for the contacting technology is prevented on operation of the component or the module.

Abstract: A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at an equivalent thermal profile in a similarly non-oxidizing ambient. The densified chemical oxide has an etch rate the same as that of thermally grown silicon dioxide in common etchants used in IC fabrication.

Abstract: An electronic component comprising at least two connection elements (2,7,8), each provided with at least one contact surface (13.1, 13.2, 13.3, 9, 10) which is used to fix the electronic component (1) to a surface of a printed circuit board. An at least partially plane cooling surface is formed on the first connection element (2), for placing on a cooling body that is oriented in the direction of the side of the electronic component (1) opposing the printed circuit board. The first connection element (2) has at least one raised area (3.1, 3.2, 3.3) on the side thereof facing the printed circuit board, on which the contact surface (13.1, 13.2, 13.1) of the first connection element (2) is formed. Said first connection element (2) also has at least one recessed area (4, 4?) in which the at least one other connection element (7, 7?; 8, 8?) is arranged.

Abstract: Tungsten-doped tin-fluorophosphate glasses are described herein which exhibit excellent humidity resistance, thermal resistance, and have a low glass transition temperature which makes them suitable for low temperature sealing applications, such as for encapsulating electronic components. In one embodiment, these glasses comprise 55-75% Sn, 4-14% P, 6-24% O, 4-22% F, and 0.15-15% W on a weight percent elemental basis.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si-NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si-NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.

Abstract: This invention comprises a process for fabricating a micro mechanical structure in a sealed cavity having a multi-layer high stiffness cap. The high stiffness material used for the cap protects the underlying microstructure from destructive environmental forces inherent in the packaging process and from environmental damage.

Abstract: An object of the invention is to provide glass for semiconductor encapsulation and an outer tube for semiconductor encapsulation which are friendly to environment and allow semiconductor electronic parts to have a heat resistance of 700° C. or higher as normal maximum temperature, and semiconductor electronic parts. The glass for semiconductor encapsulation according to the invention contains essentially no lead and the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher. According to such a constitution, since the glass contains essentially no lead, no harmful ingredients are discharged in the production of the outer tube for semiconductor encapsulation and in the production of the semiconductor electronic parts and thus the glass is friendly to environment. Moreover, since the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher, semiconductor electronic parts such as a bead thermistor using the same has a heat resistance of 700° C.

Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A manufacturing method for semiconductor devices includes a process of forming a conductive layer 4 on the other principle surface of a semiconductor wafer 10 having circuit elements 2 formed in one principle surface of the semiconductor wafer, a process of forming a protecting layer 5 on at least a part of the conductive layer, the protecting layer 5 being made from material having hard-to-shave characteristics in comparison with the conductive layer and a process of cutting the semiconductor wafer 10 into pieces with respect to each of the semiconductor devices 1. By the manufacturing method, each semiconductor device 1 is provided with a semiconductor substrate 3 having the circuit elements 2 formed in one principle surface of the semiconductor substrate 3, the conductive layer 4 formed on the other principle surface of the semiconductor substrate 3 and the protecting layer 5 formed on the conductive layer 4 in lamination to have hard-to-shave characteristics in comparison with the conductive layer 4.

Abstract: An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the middle of the frame that can absorb the mechanical stresses applied to the window frame from the ceramic base and from the window piece. The window frame may be comprised of a single piece of sheet metal that has been stamped to include a stress-relieving contour. The stress-relieving contour may be comprised of a variety of shapes, including a “U” shape, an inverted “U” shape, a curved step shape, or other combinations thereof.

Abstract: In order to fabricate a semiconductor device that can perform at its full capacity, in which (i) a single-crystal silicon integrated circuit is formed on an insulating substrate without an adhesive agent, and (ii) an active region of the single-crystal integrated circuit is not damaged by implantation of hydrogen ions, (a) the single-crystal silicon integrated circuit is formed on the insulating substrate, and (b) the single-crystal silicon integrated circuit is surrounded by an oxide (buried oxide layer made of silicon dioxide).

Abstract: An object of the invention is to provide glass for semiconductor encapsulation and an outer tube for semiconductor encapsulation which are friendly to environment and allow semiconductor electronic parts to have a heat resistance of 700° C. or higher as normal maximum temperature, and semiconductor electronic parts. The glass for semiconductor encapsulation according to the invention contains essentially no lead and the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher. According to such a constitution, since the glass contains essentially no lead, no harmful ingredients are discharged in the production of the outer tube for semiconductor encapsulation and in the production of the semiconductor electronic parts and thus the glass is friendly to environment. Moreover, since the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher, semiconductor electronic parts such as a bead thermistor using the same has a heat resistance of 700° C.

Abstract: The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

Abstract: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode material layer located over the piezoelectric material layer. The devices also include a layer of isolation material located over the second electrode material layer that at least one of chemically or electrically isolates a portion of the second electrode material layer from a fluid. Some devices include a layer of conductive material located over the layer of isolation material.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 ?. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.

Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.

Abstract: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.

Abstract: An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion is provided. According to one aspect, the window frame can be formed from a unitary piece of sheet metal. A transparent piece is attached to the inner portion of the window frame through a molding process. According to one embodiment, the window frame is placed within a mold such that the inner portion of the window frame projects into an inner cavity inside the mold. After the mold has been closed, a transparent material is injected into the inner cavity so that it bonds with the inner portion of the window frame. After the bond of between the transparent material and the window frame is set, the window frame/window piece assembly is removed from the mold. According to another embodiment, a plurality of window frames may be loaded into a single mold so that a plurality of window frame/window piece assemblies can be fabricated in a single batch.

Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si—NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si—NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.

Abstract: In one embodiment, a package for a micro-device includes a substrate, a transparent material covering the substrate, and a bond ring bonding the transparent material to the substrate. The bond ring comprises a silicon oxide layer on one of the substrate or the transparent material bonded to a silicon layer on the other of the substrate or the transparent material.