Abstract: A projector includes a semiconductor die including a digital micromirror device; and a first integral optical layer attached to the semiconductor die. The first integral optical layer includes a first optical lens and a first diffractive optical element. A second integral optical layer is attached to the first integral optical layer. The second integral optical layer includes an aperture stop and a second diffractive optical element. A third integral optical layer is attached to the second integral optical layer. The third integral optical layer includes a second optical lens and a light source mount. The semiconductor die, the first integral optical layer, the second integral optical layer and the third integral optical layer are stacked to form an optical path through the first and second diffractive optical elements, reflect off the digital micromirror device, and pass through the first optical lens, the aperture stop and the second lens.

Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.

Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed.

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract: A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.

Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.

Abstract: A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract: A resin molding mold 20 with a cavity 21 has a resin injection port 29a from which a molding resin 25 is injected toward the cavity 21, and an air release port 30a from which air from the cavity 21 is released during resin injection. Not only the resin injection port 29a but also the air release port 30a is formed in a top surface portion 21a of the cavity 21. Thus, even if a resin burr remains in the resin injection port 29a or the air release port 30a, it can be prevented from adhering to an external terminal 4A provided on a front surface portion 2a of the substrate 2.

Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).

Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.

Abstract: A method of forming a passivation layer comprises contacting at least one surface of a wide band-gap semiconductor material with a passivating agent comprising an alkali hypochloride to form the passivation layer on said at least one surface. The passivation layer may be encapsulated with a layer of encapsulation material.

Abstract: A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave plasma-enhanced chemical vapor deposition by exposing the germanium material to a microwave-generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed.

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.

Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying the temperature within a reaction chamber while a layer of a material is formed upon the semiconductor substrate. Varying the temperature within the reaction chamber facilitates temperature uniformity across the semiconductor wafer. As a result, a layer forming reaction occurs at a substantially consistent rate over the entire active surface of the semiconductor substrate. The process may also include oscillating the temperature within the reaction chamber while a layer of a material is being formed upon a semiconductor substrate.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: A semiconductor component includes a semiconductor chip provided with a passivation layer that covers the topmost interconnect structure of the semiconductor chip whilst leaving contact areas free. The passivation layer is in direct adhesive contact with the plastic housing composition of the semiconductor component. The passivation layer includes a polymer with embedded mineral-ceramic nanoparticles.

Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states include reduction or elimination of an electrically active state of the surface, wherein, at the atomic level, the surface binding characteristics are changed. Passivation includes the termination of dangling bonds on the surface of the semiconductor material.

Abstract: A CMOS type of image sensor module for use in a mobile camera or a PC camera includes an image sensoring semiconductor chip encapsulated in a transparent block of polymeric material on a substrate having a circuit to which the ship is connected. The image sensoring semiconductor chip is disposed on an upper surface of the substrate as spaced vertically from a digital signal processing second semiconductor chip mounted on a lower surface of the substrate. The transparent polymeric encapsulation material constitutes a sealing resin unit. The digital signal processing second semiconductor chip may also be encapsulated by the sealing resin unit. The sealing transfer unit can be formed by injection and/or transfer molding. The forming of the sealing resin unit by a single molding process keeps production costs low.

Abstract: The invention is directed to a surface acoustic wave sensor assembly that makes use of a Z-axis conductive layer, such as a Z-axis conductive elastomer, or the like. In particular, a Z-axis conductive elastomer couples a circuit layer to a surface acoustic wave (SAW) sensor in order to form a SAW sensor assembly. For example, a plurality of electrical contacts of the circuit layer can be coupled to a plurality of electrodes of the SAW sensor via the Z-axis conductive elastomer. The Z-axis conductive elastomer provides electrical coupling between the electrical contacts and the electrodes, and also forms a hermetic barrier between the circuit layer and the SAW sensor. In addition, elastic properties of the Z-axis conductive elastomer may reduce pressure exerted on the SAW sensor during use.

Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: An electronic package for a photo-sensing device is provided. The package is formed to include a substrate of a material substantially transparent to light within a predetermined range of wavelengths. The package further formed to include at least one photo-sensing die having a photo-sensing area defined on a front side thereof. The photo-sensing die is mounted to the substrate by a plurality of interconnection joints disposed about the photo-sensing area, whereby the front side of the photo-sensing die is spaced by a gap from a front surface of the substrate. A sealing structure is formed to extend about the interconnection joints to fill portions of the gap thereabout, such that the sealing structure contiguously encloses an internal cavity in substantially sealed manner between the photo-sensing die and substrate. This internal cavity communicates with the photo-sensing area of the photo-sensing die.

Abstract: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.

Abstract: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer, plasma-treating the PEFSG layer, and forming a second SRO layer on the plasma-treated PEFSG layer. According to the present invention, the thickness of the second SRO layer of the inter-metal dielectric can be reduced. Consequently, process cost can be reduced, and the total thickness of the inter-metal dielectric can be reduced so as to lower the dielectric constant thereof, reduce the aspect ratio of any via holes that are subsequently formed in the inter-metal dielectric, and potentially increase the yield as a result of the reduced via hole aspect ratio.

Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.

Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present inention.

Abstract: A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cerium oxide and titanium oxide. The dielectric materials can be incorporated into any suitable semiconductor devices, including, for example, capacitor devices, transistor devices, and flash memory devices. The invention also includes methods of utilizing atomic layer deposition to form laminates of cerium oxide and titanium oxide.

Abstract: The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one embodiment of the invention, first of all a layer sequence of a first oxide layer, a first nitride layer and a second oxide layer is disposed onto the substrate. Subsequently, a portion of the second oxide layer and a portion of the first nitride layer is removed in order to expose a portion of the first oxide layer. Then, a part of the first nitride layer above the first oxide layer and below the second oxide layer is removed in order to expose the area of the structure.