Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.

Abstract: An aircraft electrical system includes a controller system having a self-testing system configured to test an operability of a transient voltage suppression device. A single line communication bus is connected to a communications output of the controller. A first lightning protection device including the transient voltage suppression device is configured to protect the controller from transient voltages. An enable/disable circuit comprising a normally closed switch connects a low side of the lightning protection device to a neutral.

Abstract: An electronic device can include a channel layer and a barrier layer overlying the channel layer. In an embodiment, the electronic device can include a component disposed along a current path between a gate terminal and a gate electrode of a first transistor. In another embodiment, the electronic device can include a second transistor wherein source and gate electrodes of the second transistor are coupled to the gate electrode of the first transistor, and a drain electrode of the second transistor is coupled to the gate terminal. A circuit can include a transistor and a diode. The transistor can include a drain, a gate, and a source, wherein the drain is coupled to a drain terminal, and the source is coupled to a source terminal. The diode can have an anode is coupled to the gate terminal, and a cathode is coupled to a gate of the transistor.

Abstract: A front end module includes a transmitter path network coupled to an antenna and a transmitter, and includes a first selectable matching network. The front end module further includes a receiver path network coupled to the antenna and a receiver. The receiver path network is a second selectable matching network.

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract: A fuse of a semiconductor device and a method for forming the same are disclosed. The fuse includes a first metal line formed over a semiconductor substrate, a second metal line spaced apart from the first metal line, and a contact fuses formed of a metal contact coupled to the first metal line and the second metal line. Upper parts of the contact fuses overlap with each other, and lower parts are spaced apart from each other. Since the fuse is formed of a metal contact, fuse oxidation and fuse movement can be prevented. A conventional metal-contact fabrication process can be used, so that mass production of semiconductor devices is possible. In addition, the fuse region is reduced in size, reducing production costs.

Abstract: An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.

Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

Abstract: A semiconductor device includes: a semiconductor element (1) having an internal circuit (17); and electrode pads (22, 22, . . . ) provided for the semiconductor element (1). The electrode pads (22, 22, . . . ) are electrically connected to the internal circuit (17) via control portions (31) for controlling electrical connection between the electrode pads (22, 22, . . . ) and the internal circuit (17).

Abstract: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.

Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Abstract: Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.

Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.

Abstract: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Abstract: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: Programmable via devices and methods for the fabrication thereof are provided.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.

Abstract: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.

Abstract: A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.

Abstract: Example embodiments of the present invention relate to an alloy solder and a semiconductor device using the alloy solder. Other example embodiments relate to an alloy solder capable of increasing reliability of a junction between a semiconductor chip and a substrate. According to still In still other example embodiments of the present invention, there may be a tin-bismuth (Sn—Bi) family alloy solder between a semiconductor chip and a substrate, and a semiconductor device using the alloy solder. The semiconductor device may include a semiconductor chip formed with a plurality of gold bumps, a substrate having metal wirings connected to the gold bumps, and a junction including a tin-bismuth family alloy solder interposed between and connecting the gold bump and the metal wiring.

Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.

Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: A structure and method of forming a metal buffering layer during the formation of a redistribution layer is provided. It only changes a mask to form the metal buffering layer and circuit traces simultaneously. The metal buffering layer can increase the flatness of the dielectric layer covering on the metal buffering layer. It can also make the structure under the metal buffering layers suffer uniform pressure to prevent the passivation layer from cracking and the circuit traces from collapsing in order to increase the yield of the packaged chips.