Cross-sectional Geometry (epo) Patents (Class 257/E23.152)
  • Patent number: 10763207
    Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Ganesh Hegde, Harsono Simka
  • Patent number: 9590057
    Abstract: A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9536877
    Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: January 3, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Xiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9343400
    Abstract: A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions of the first conductive layer outside the plurality of first openings, the patterned mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings. A second conductive layer is filled in the plurality of second openings. The patterned mask layer is removed to leave behind the conductive layer structures on the substrate. The substrate is heated to form a self-forming barrier layer on the top and sidewalls of the conductive layer structures.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 8981547
    Abstract: A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8884444
    Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nitta
  • Patent number: 8860226
    Abstract: A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Won Seo
  • Patent number: 8860225
    Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
  • Patent number: 8836135
    Abstract: A semiconductor device including: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Kikuchi
  • Patent number: 8810040
    Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 8786099
    Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 8759985
    Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: June 24, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Daryl Fox, Scott T. Becker
  • Patent number: 8648471
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tabata, Eiji Ito, Hirofumi Inoue
  • Patent number: 8648402
    Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Seung-Uk Han, Nam-Ho Jeon
  • Patent number: 8629550
    Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: January 14, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Takashi Kariya, Yoji Mori
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8614511
    Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukhun Choi, Kyunghyun Kim, ChangSup Mun, Byoungkeun Son
  • Patent number: 8604557
    Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Narumi Ohkawa
  • Patent number: 8597960
    Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, Michael Ignatowski
  • Patent number: 8541819
    Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 24, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
  • Patent number: 8541878
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 24, 2013
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 8513815
    Abstract: A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Aipperspach, Todd A. Christensen, John E. Sheets, II
  • Patent number: 8513778
    Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 20, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shunichi Tokitoh
  • Patent number: 8502321
    Abstract: A semiconductor device including first and second transistors having first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface of the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom surface in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than a longitudinal direction width of the first bottom surface. A high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom surface in the longitudinal direction are larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Izumi, Kikuko Sugimae, Hiroyuki Kutsukake, Keisuke Yonehama
  • Patent number: 8476763
    Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, In-Sun Park, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee, Jong-Won Hong
  • Patent number: 8471391
    Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: June 25, 2013
    Assignee: Tela Innovations, Inc.
    Inventors: Daryl Fox, Scott T. Becker
  • Patent number: 8441111
    Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: May 14, 2013
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8436457
    Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 7, 2013
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8378448
    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Wayne H. Woods, Jr.
  • Patent number: 8344497
    Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Eun-Chul Ahn, Teak-Hoon Lee, Chul-Yong Jang
  • Patent number: 8319329
    Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-kyu Kang, Jung-Ho Kim, Jong-Wook Lee, Seung-woo Choi, Dae-Lok Bae
  • Patent number: 8310056
    Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Oda, Shinichi Chikaki
  • Patent number: 8258628
    Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Patent number: 8253198
    Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 28, 2012
    Assignee: Micron Technology
    Inventor: Toru Tanzawa
  • Patent number: 8207613
    Abstract: A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: June 26, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Okukawa, Satoru Takase
  • Patent number: 8183602
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tabata, Eiji Ito, Hirofumi Inoue
  • Patent number: 8183148
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Aburada, Hiromitsu Mashita, Toshiya Kotani, Chikaaki Kodama
  • Patent number: 8115316
    Abstract: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the pad electrode; and a joint layer formed on the pad electrode inside the opening. The surface of the joint layer is lower than the top lip of the opening.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: February 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Takeshi Nakamura, Yusuke Igarashi
  • Publication number: 20120018863
    Abstract: A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via.
    Type: Application
    Filed: July 23, 2010
    Publication date: January 26, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 8076781
    Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: December 13, 2011
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
  • Patent number: 8072066
    Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: December 6, 2011
    Assignee: OmniVision Technologies, Inc.
    Inventors: Liang Tan, Herbert J. Erhardt
  • Patent number: 8072080
    Abstract: The invention provides a connection structure including: a first electro-conductive film that is formed on a substrate; an insulation film that is formed on the first electro-conductive film, an end surface of the insulation film facing in a direction in which an end surface of the first electro-conductive film faces; and a second electro-conductive film that extends from the upper surface of the insulation film to reach the end surface of the first electro-conductive film across the end surface of the insulation film, the second electro-conductive film being electrically connected to the first electro-conductive film via the end surface of the first electro-conductive film.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 6, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Moriwaki
  • Publication number: 20110266698
    Abstract: A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed.
    Type: Application
    Filed: April 5, 2011
    Publication date: November 3, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Keun-bong LEE
  • Patent number: 8044517
    Abstract: An electronic component comprises a plurality of layers at least two of which comprise predominantly organic functional materials with improved through-plating through certain of the layers. The through-plating is formed in one embodiment by a disruption element on a first lower layer which results in a void in the subsequently applied layers, which void is filled with a material which may be conductive to form the through plating. In a second embodiment, the through plating is formed on the first lower layer prior to the subsequent application of the other layers, in the form of a free-standing truncated frusto-conical raised portion, and forms a disruption or non-welting element for the subsequently applied other layers, formed on the first lower layer and which are engaged with and surround the through plating after their application.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: October 25, 2011
    Assignee: PolyIC GmbH & Co. KG
    Inventors: Wolfgang Clemens, Adolf Bernds, Alexander Friedrich Knobloch
  • Patent number: 8013423
    Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 6, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong-Yeal Keum
  • Patent number: 8008729
    Abstract: An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: August 30, 2011
    Assignee: Qimonda AG
    Inventors: Werner Graf, Clemens Fitz
  • Publication number: 20110198761
    Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.
    Type: Application
    Filed: April 12, 2011
    Publication date: August 18, 2011
    Applicant: Tela Innovations, Inc.
    Inventors: Daryl Fox, Scott T. Becker
  • Patent number: 7994047
    Abstract: An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: August 9, 2011
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Ning Cheng, Huade Walter Yao
  • Patent number: 7948087
    Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 24, 2011
    Assignee: Advantech Global, Ltd
    Inventor: Thomas Peter Brody
  • Patent number: 7948088
    Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: May 24, 2011
    Assignees: Hitachi, Ltd., Honda Motor Co., Ltd.
    Inventors: Toshio Saito, Satoshi Moriya, Morio Nakamura, Goichi Yokoyama, Tatsuyuki Saito, Nobuaki Miyakawa