Including Internal Interconnections, E.g., Cross-under Constructions (epo) Patents (Class 257/E23.168)
  • Patent number: 7994545
    Abstract: Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 9, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 7977770
    Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: July 12, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Se-Yeul Bae
  • Patent number: 7977778
    Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Publication number: 20110156163
    Abstract: This invention disclosed a kind of electrode picking up structure in LOCOS isolation process. The active region is isolated by local oxide of silicon (LOCOS). A pseudo buried layer under the bottom of LOCOS is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. This is achieved by deep trench contacts which etch through LOCOS and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 30, 2011
    Inventors: Tzuyin CHIU, TungYuan Chu, YungChieh Fan, Wensheng Qian, Jiong Xu, Fan Chen, Haifang Zhang
  • Patent number: 7968451
    Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao, Chen-Hua Yu
  • Publication number: 20110147915
    Abstract: A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first supply in top metal and a second contiguous FDM array of a second supply in top-1 metal, a third contiguous FDM array of the second supply in top metal and a fourth contiguous FDM array of the first supply in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by VIAs and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by VIAs and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Aparna Ramachandran, Robert P. Masleid
  • Publication number: 20110140279
    Abstract: Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer).
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robinson
  • Publication number: 20110127649
    Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.
    Type: Application
    Filed: September 9, 2010
    Publication date: June 2, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Kwon-Seob Lim
  • Publication number: 20110115091
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 19, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kenichi Watanabe
  • Publication number: 20110115073
    Abstract: A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 19, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsien-Wei Chen
  • Publication number: 20110108985
    Abstract: A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillar patterns; depositing an insulating layer on the surface of the pillar pattern; removing a portion of the insulating layer located at one side of the pillar pattern to form a contact hole that exposes the pillar pattern; forming a barrier film in the contact hole; and forming a junction in the pillar pattern that contacts with the contact hole. In the method, when a buried bit line is formed, a diffusion barrier is formed in the contact hole and a junction is formed in the lower portion of the pillar pattern, thereby improving characteristics of the device.
    Type: Application
    Filed: June 15, 2010
    Publication date: May 12, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Seung Hwan KIM
  • Publication number: 20110101445
    Abstract: A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure.
    Type: Application
    Filed: October 12, 2010
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-Uk Kim, Yong-Chul Oh, Hui-Jung Kim, Hyun-Woo Chung, Hyun-Gi Kim
  • Patent number: 7935621
    Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Publication number: 20110095433
    Abstract: There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers.
    Type: Application
    Filed: October 21, 2010
    Publication date: April 28, 2011
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Michio HORIUCHI, Yasue TOKUTAKE, Yuichi MATSUDA, Tsuyoshi KOBAYASHI, Tatsuaki DENDA
  • Patent number: 7932606
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: April 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Publication number: 20110084397
    Abstract: A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 14, 2011
    Applicant: Macronix International Co., Ltd.
    Inventor: HSIANG-LAN LUNG
  • Publication number: 20110084410
    Abstract: A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 14, 2011
    Inventor: Tae-Sung Yoon
  • Publication number: 20110079922
    Abstract: A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Hao-Yi Tsai, Hsien Wei Chen, Hsiu-Ping WEI
  • Publication number: 20110074044
    Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qinghuang Lin, Deborah A. Neumayer
  • Publication number: 20110073997
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, the method including: forming a first conductive interconnect at least partially through the substrate; and forming a second conductive interconnect over the substrate, wherein the first conductive interconnect and the second conductive interconnect are formed at least partially simultaneously.
    Type: Application
    Filed: September 28, 2009
    Publication date: March 31, 2011
    Inventors: Rainer LEUSCHNER, Gunther MACKH, Uwe SEIDEL
  • Patent number: 7911063
    Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Terazono, Katsuhiko Akao
  • Publication number: 20110062589
    Abstract: A semiconductor device has: a semiconductor substrate formed with a plurality of semiconductor elements, a plurality of interlevel insulating films laminated above the semiconductor substrate, including a first and a second interlevel insulating films adjacent to each other; a first wiring trench formed in the first interlevel insulating film; and a first damascene wiring including: a first barrier metal film having a diffusion preventive function, formed covering inner surface of the first wiring trench and defining a first main wiring trench; and a first main wiring layer filling the first main wiring trench, formed of first metal element, and added with second metal element having migration suppressing function, at spatially different concentration.
    Type: Application
    Filed: November 19, 2010
    Publication date: March 17, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Hideki Kitada
  • Publication number: 20110042795
    Abstract: Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections.
    Type: Application
    Filed: August 20, 2009
    Publication date: February 24, 2011
    Applicant: International Business Machines Corporation
    Inventor: John U. Knickerbocker
  • Publication number: 20110042832
    Abstract: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance.
    Type: Application
    Filed: November 3, 2010
    Publication date: February 24, 2011
    Inventors: Peter Peumans, Kevin Huang, Fu-Kuo Chang
  • Patent number: 7892918
    Abstract: A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Yoon Lee, Hyuck-Chai Jung
  • Publication number: 20110031621
    Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
    Type: Application
    Filed: October 22, 2010
    Publication date: February 10, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Soo Chung, Ho-Jin Lee, Dong-Hyun Jang, Dong-Ho Lee
  • Publication number: 20110012270
    Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 20, 2011
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Patent number: 7872355
    Abstract: A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring layers and overlap with each other at a plurality of intersections; and vias connecting the plurality of first power wirings and the plurality of second power wirings. The circuit group includes a first functional block placed on a first region. The vias are not placed at a part of the plurality of intersections within a second region located between the first region and the power pad.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kouji Owa
  • Publication number: 20100327407
    Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches.
    Type: Application
    Filed: November 9, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Chun Soo Kang
  • Publication number: 20100327467
    Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Keisuke Hirabayashi
  • Publication number: 20100327445
    Abstract: An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald Filippi, Wai-kin Li, Ping-Chuan Wang
  • Publication number: 20100314764
    Abstract: A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Kaushik Chanda, Daniel Edelstein, Baozhen Li
  • Publication number: 20100314771
    Abstract: A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line.
    Type: Application
    Filed: March 15, 2010
    Publication date: December 16, 2010
    Inventors: Yoshikazu HOSOMURA, Toshiki Hisada, Fumiharu Nakajima, Chikaaki Kodama
  • Publication number: 20100314689
    Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JEFFERY B. MAXSON, AURELIA A. SUWARNO-HANDAYANA, SHAMAS M. UMMER, KENNETH J. GIEWONT, SCOTT RICHARD STIFFLER
  • Publication number: 20100314768
    Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: International Business Machines Corporation
    Inventors: Maxime Darnon, Jeffrey P. Gambino, Elbert E. Huang, Qinghuang Lin
  • Patent number: 7847416
    Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, In-Young Lee, Son-Kwan Hwang, Dong-Ho Lee, Seong-Deok Hwang
  • Publication number: 20100301490
    Abstract: A profiled contact for a device, such as a high power semiconductor device is provided. The contact is profiled in both a direction substantially parallel to a surface of a semiconductor structure of the device and a direction substantially perpendicular to the surface of the semiconductor structure. The profiling can limit the peak electric field between two electrodes to approximately the same as the average electrical field between the electrodes, as well as limit the electric field perpendicular to the semiconductor structure both within and outside the semiconductor structure.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 2, 2010
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 7843068
    Abstract: A semiconductor chip includes a semiconductor substrate 11, a through via 12 provided in a through hole 17 that passes through the semiconductor substrate 11, insulating layers 21-1 to 21-3 laminated on the semiconductor substrate 11, a multi-layered wiring structure 14 having a first wiring pattern 22 and a second wiring pattern 23, and an external connection terminal 15 provided on an uppermost layer of the multi-layered wiring structure 14, wherein the through via 12 and the external connection terminal 15 are connected electrically by the second wiring pattern 23.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: November 30, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi
  • Patent number: 7838395
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: November 23, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Patent number: 7838992
    Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Ho-Jin Lee, Dong-Hyun Jang, Dong-Ho Lee
  • Publication number: 20100283160
    Abstract: A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 11, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventor: Arvind Chandrasekaran
  • Publication number: 20100276809
    Abstract: T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: International Business Machines Corporation
    Inventors: Hanyi Ding, Essam Mina, Guoan Wang, Wayne Harvey Woods, JR.
  • Patent number: 7812451
    Abstract: A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides of the wiring layer. An air bridge wiring intersects the second and third wiring layers sandwiching an air layer above the first wiring layer therewith. The overall shape of the air bridge wiring has an upward convex curvature in an arch shape and the transverse sectional shape of the air bridge wiring is in the form of a downward concave curvature.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Asano
  • Publication number: 20100252896
    Abstract: Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.
    Type: Application
    Filed: June 11, 2010
    Publication date: October 7, 2010
    Applicant: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 7800184
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: September 21, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 7790600
    Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: September 7, 2010
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Pierre Jacobs, Bert Sels, Jasper Van Noyen, Caroline Whelan, Karen Maex, Filip de Clippel
  • Publication number: 20100213515
    Abstract: An integrated circuit may include one or more cells, with each cell comprising a first and a second input terminal, a first and a second output terminal, and a number of connection stages configured to couple each input terminal to a corresponding respective output terminal. The stages may include one stage per metal layer of the integrated circuit and one stage per VIA layer of the integrated circuit. Each stage may be configured with a pair of input ports and a pair of output ports. Each output port of a stage may serially connect to a corresponding respective input port of a first adjacent stage, and each input port of the stage may also serially connect to a corresponding respective output port of a second adjacent stage. The pair of input ports may also be configured to programmably connect to the pair of output ports within the same stage, according to one of two different connection patterns, to establish a respective connection within the stage.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Inventors: Antonio S. Lopes, Steven Burstein
  • Publication number: 20100213607
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple Microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the Microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate.
    Type: Application
    Filed: June 5, 2009
    Publication date: August 26, 2010
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peter SMEYS, Peter JOHNSON, Peter DEANE
  • Patent number: 7781889
    Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: August 24, 2010
    Assignee: Intel Corporation
    Inventors: Bram Leader, Richard R. Doersch
  • Publication number: 20100200948
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.
    Type: Application
    Filed: June 26, 2009
    Publication date: August 12, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Se hyun KIM