Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.

Abstract: Molecules of a coupling layer composition in a semiconductor device are bidimensionally polymerized in order to provide enhanced moisture blocking effect, particularly when the coupling layer is formed on a porous layer, such as a porous dielectric layer. The deposition of the coupling layer on the underlying structure and/or the cross-polymerization of the coupling layer composition and/or a final metallization can be photo-activated, especially, but not only, using an ultraviolet light.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film.

Abstract: A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2, semiconductor chip 3a stacked on substrate 4 together with semiconductor chip 2, and having a foot print larger than semiconductor chip 2, through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2, through electrode 32 extending through semiconductor chip 3a at a position facing to through electrode 22, and conduction bump 7b arranged between through electrode 22 and through electrode 32, and conductively connecting through electrode 22 with through electrode 32.

Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.

Abstract: The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material mainly composed of Cu, penetrating through the intermediate dielectric film to be connected to the first wire and the second wire; and a dummy via, made of a material mainly composed of Cu, smaller in via diameter than the via and connected to the first wire while not contributing to electrical connection between the first wire and the second wire.

Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.

Abstract: A thin film panel is provided, which includes a first signal line and a second signal line crossing the first signal line and formed on a different layer from the first signal line. The second signal line includes an expansion having an enlarged area and at least one cutout, and is disposed adjacent to a crossing region where the second signal line crosses the first signal line.

Abstract: An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads respectively, wire bonds electrically connecting each of the contact pads to the corresponding conductors and, an adhesive surface positioned between the contacts pads and the corresponding conductors. The wire bonds are secured to the adhesive surface to hold them in a low profile configuration.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a circuit layer, a metal interconnection layer, and a deep via. The circuit layer is formed on a semiconductor substrate. The metal interconnection layer is formed on the circuit layer. The metal interconnection layer comprises a metal interconnection connected to the circuit layer. The deep via penetrates through the semiconductor substrate and the metal interconnection layer. The deep via comprises a laser-annealed crystalline silicon.

Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.

Abstract: A power semiconductor module comprising: a substrate, a plurality of conductor tracks arranged thereon, the conductor tracks being electrically insulated from one another, and including power semiconductor components arranged thereon; a connecting device, composed of an alternating layer sequence of at least two electrically conductive layers and at least one electrically insulating layer disposed therebetween, for the circuit-conforming connection of the power semiconductor components, the conductor tracks and/or external contact devices. The electrically conductive layers form connecting tracks and at least one transformer is formed integrally with, and thus from the constituent parts of, the connecting device. The transformer is composed of at least one transmitter coil and at least one receiver coil, which are in each case arranged coaxially with respect to one another and are formed with spiral windings.

Abstract: An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.

Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

Abstract: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the copper layer.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoB2 layer, an MoxByNz layer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract: An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoxOy layer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A semiconductor device which comprises an SOI substrate having an insulating layer between a semiconductor substrate layer and a semiconductor layer in a surface of which a semiconductor element is formed, and at least one external terminal provided, via an insulating film, on a surface of the semiconductor substrate layer and electrically connected to the semiconductor element. The semiconductor device further comprises a contact portion constituted by a conductive film reaching through the insulating film to electrically connect to the semiconductor substrate layer; and a potential fixing electrode provided, via the insulating film, on the surface of the semiconductor substrate layer and connected to the contact portion.

Abstract: Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal layer on the epitaxial stack. Accordingly, in accordance with the present invention, the contact plug is selectively doped in a high concentration, thereby reducing a contact resistance. Furthermore, the present invention also provides an effect of reducing degradation in a device property without decreasing yields of products by minimizing a thermal budget through using a SEG-silicon germanium layer capable of obtaining a high doping concentration and a high deposition speed.

Abstract: A semiconductor device includes an interlayer insulating film, a barrier metal layer, a conductive layer and a first insulating film. The barrier metal layer is formed on a bottom surface and a side face of a trench made in the interlayer insulating film. The conductive layer is formed on the barrier metal layer. The conductive layer has its upper surface lower than an upper surface of an opening of the trench and buries a part of the trench. The first insulating film is formed on the conductive layer and is formed on the barrier metal layer on a side face of the opening of the trench. The first insulating film is made of a material having a dielectric constant higher than that of the interlayer insulating film.

Abstract: An etching stopper film is formed on top of a first insulating film. The etching stopper film is a film formed by depositing at least two films, made of constituent materials identical in quality to each other, one another. Subsequently, a first opening pattern is formed in the etching stopper film. Subsequently, a second insulating film is formed on top of the etching stopper film. Subsequently, a mask pattern is formed on top of the second insulating film. Subsequently, the second insulating film is etched with the use of the mask pattern as a mask to be followed by etching of the first insulating film with the use of the etching stopper film as a mask.

Abstract: Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

Abstract: There is provided a semiconductor device including a semiconductor substrate on which a plurality of semiconductor chips having electrode pads is formed, an internal connection terminal provided on each of the electrode pads, an insulating layer provided to cover the plurality of semiconductor chips and the internal connection terminals, and a wiring pattern connected to the internal connection terminals across the insulating layer. This semiconductor device is characterized in that the insulating layer is configured to contain an alpha ray blocking material including polyimide and/or a polyimide-based compound.

Abstract: A semiconductor device includes: a metal-containing compound layer on a semiconductor substrate; a dielectric film on the semiconductor substrate and the metal-containing compound layer; a contact hole penetrating through the dielectric film to reach the metal-containing compound layer; a contact plug in the contact hole. The semiconductor device further includes a manganese oxide layer extending between the contact plug and respective one of the dielectric film and the metal-containing compound layer.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: A method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate of a vertical transistor. As a result, the yield and reliability of the semiconductor device can be improved.

Abstract: According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.

Abstract: A method of manufacturing a semiconductor device including a trench and a contact hole filled with a copper line, a diffusion barrier layer formed in inner walls of the trench and the contact hole, and a seed-copper layer formed on and/or over the diffusion barrier layer. The surface roughness of the seed-copper layer can be reduced by performing a plasma process thereon.

Abstract: An interconnection system is provided for a solid-state device. The solid-state that includes, a first layer, multiple devices and a first face. A second layer is bonded to the first face at a bonded face of the second layer that faces the first face. Electrically conductive bonds are between the first and second faces. Conductive paths are on the bonded face of the second layer and connect two or more of the conductive bonds.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

Abstract: A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction.

Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.

Abstract: A lead frame including a stage and a plurality of terminals is embedded in a mold resin including a base portion for mounting a semiconductor chip (e.g. a microphone chip), a peripheral wall disposed in the periphery of the base portion, and an extension portion extended outside of the peripheral wall, thus forming a package base. A plurality of holes is formed in the peripheral wall so as to expose the internal connection surface of the stage and the internal connection surfaces of the terminals. An extension portion of the stage is exposed on the extension portion of the mold resin in which the surfaces of the terminals are embedded. An extension portion (e.g. a brim) of a cover composed of a conductive material is attached to the extension portion of the mold resin of the package base, thus completely producing a semiconductor device.

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.

Abstract: A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection.

Abstract: Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating coats a surface of the dielectric layer in the first opening. An electrically insulating material substantially fills the first opening. The circuit board includes a first additional dielectric layer attached to the first planar surface, and a second additional dielectric layer attached to the second planar surface. A second opening extends through the first additional dielectric layer, the electrically insulating material filling the first opening, and the second additional dielectric layer.

Abstract: An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data line lead, and a passivation layer, which are formed sequentially in the lead region on the substrate. The gate layer data line segment extends corresponding to the data line lead; the data line lead is formed with a via hole therein; a portion of the gate insulating layer and a portion of the passivation layer in a position corresponding to the via hole are removed so as to form a connection hole together with the via hole; a connection line segment is formed in the connection hole, and the gate layer data line segment and the data line lead are connected by the connection line segment in the connection hole.

Abstract: Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

Abstract: A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic component mounting surface of a wiring board body and so that an air gap is kept between a portion of the external connection terminal, to which the electrode terminal of the electronic component is to be connected, and the insulating layer.

Abstract: In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure with the passivation layer.

Abstract: Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.