Characterized By Shape Of Container Or Parts, E.g., Caps, Walls (epo) Patents (Class 257/E23.181)
  • Patent number: 8269320
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rui Huang, Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan
  • Publication number: 20120228756
    Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Inventors: Tobias KOLLETH, Pascal Stumpf, Christian Joos
  • Patent number: 8247889
    Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 21, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hsien Liao, Jian-Cheng Chen
  • Patent number: 8247897
    Abstract: A blank and a semiconductor device are include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: August 21, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Edward Fuergut
  • Publication number: 20120187553
    Abstract: A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting the spacer formation layer to exposure and development to be patterned and removing the support base; and a step of bonding a transparent substrate to a region of the spacer where the removed support base was provided so that transparent substrate is included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably.
    Type: Application
    Filed: September 8, 2010
    Publication date: July 26, 2012
    Applicant: SUMITOMO BAKELITE COMPANY LIMITED
    Inventors: Masahiro Yoneyama, Masakazu Kawata, Toyosei Takahashi, Hirohisa Dejima, Fumihiro Shiraishi, Toshihiro Sato
  • Publication number: 20120161309
    Abstract: A semiconductor package includes a base portion including a first member and a second member which are joined to each other; a semiconductor element mounted on the first member; a terminal mounted on the second member; and a wire electrically connecting the semiconductor element to the terminal. Heat resistance of the first member is lower than heat resistance of the second member, and linear thermal expansion coefficient of the second member is smaller than linear thermal expansion coefficient of the first member.
    Type: Application
    Filed: July 11, 2011
    Publication date: June 28, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hiromitsu UTSUMI
  • Patent number: 8207022
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: June 26, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Publication number: 20120126391
    Abstract: Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 24, 2012
    Applicant: IMEC
    Inventors: Alain Phommahaxay, Lieve Bogaerts, Philippe Soussan
  • Publication number: 20120119349
    Abstract: An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains ?-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride.
    Type: Application
    Filed: July 15, 2010
    Publication date: May 17, 2012
    Applicants: TOSHIBA MATERIALS CO., LTD., KABUSHIKI KAISHA TOSHIBA
    Inventor: Takayuki Naba
  • Publication number: 20120098074
    Abstract: The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided.
    Type: Application
    Filed: October 21, 2010
    Publication date: April 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 8164180
    Abstract: A functional element package includes a silicon substrate with a functional element having one of a mobile portion and a sensor thereon; a seal member being bonded with the silicon substrate to form an airtightly sealed space therein, and including a step portion in its height direction; a first wiring portion being connected with the functional element and extending from the airtightly sealed space to an outside thereof; a second wiring portion being different from the first wiring portion and extending from the step portion to an upper surface of the seal member; and a bump on the second wiring portion, in which the first wiring portion is bent towards the airtightly sealed space and connected via a photoconductive member with the second wiring portion on the step portion.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: April 24, 2012
    Assignees: Ricoh Company, Ltd., Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Yukito Sato, Joerg Froemel
  • Publication number: 20120086116
    Abstract: An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.
    Type: Application
    Filed: August 30, 2011
    Publication date: April 12, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuichi TAGUCHI, Akinori Shiraishi, Mitsutoshi Higashi
  • Patent number: 8154113
    Abstract: An interconnect includes an elastic body, an electric conductor and a spacer. The elastic body has a first surface, a second surface, a first hole extending from the first surface to the second surface, and a second hole extending from the first surface to the second surface. The electric conductor is disposed in the first hole of the insulating body for contacting one of a plurality of balls of the first integrated circuit package and one of a plurality of conductor pads of the second integrated circuit package. The electric conductor includes an elastic body and electric conductor particles disbursed in the elastic body. The spacer is disposed in the second hole.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: April 10, 2012
    Assignee: Yamaichi Electronics USA, Inc.
    Inventors: Jesus S. Sangalang, Kazuya Takahashi
  • Publication number: 20120080784
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: SURESH D. KADAKIA, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 8148811
    Abstract: This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate 2, and exposure to transfer a pattern is performed. By subsequent development and selective removal of the resist layer, the resist layer is formed into a shape of a plurality of columnar structures 4. Then, an adhesive material made of an epoxy resin or the like is applied to the entire top surface of the semiconductor substrate 2. The adhesive material is gathered around the columnar structures 4 by itself to form an adhesive layer 5. Therefore, in contrast, the adhesive layer 5 does not deposit in a region where the cavity is to be formed. Then, the supporting member 6 is bonded through the columnar structures 4 and the adhesive layer 5.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: April 3, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.
    Inventors: Hiroyuki Shinogi, Katsuhiko Kitagawa, Kazuo Okada, Hiroshi Yamada
  • Publication number: 20120074555
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Publication number: 20120074560
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Hin Hwa Goh, Xusheng Bao, Yung Kuan Hsiao, Kang Chen, Rui Huang
  • Publication number: 20120074538
    Abstract: A package structure with ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a carrier having first and second ground structures electrically insulated from one another; a semiconductor component disposed on one surface of the carrier and electrically connected to the first ground structure; and a lid member disposed to cover the carrier and the semiconductor component and electrically connected to the second ground structure. The semiconductor component and the lid member are electrically connected with the first ground structure and the second ground structure, respectively, such that electrostatic charges and electromagnetic waves can be conducted away individually without damaging the semiconductor component, thereby improving yield and reducing the risk of short circuits.
    Type: Application
    Filed: October 28, 2010
    Publication date: March 29, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Tsung-Hsien Tsai, Heng-Cheng Chu, Hsin-Lung Chung, Chao-Ya Yang
  • Patent number: 8143729
    Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 27, 2012
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
  • Publication number: 20120068324
    Abstract: A semiconductor device includes at least two or more groups of external connection terminals to which a substrate that drives a bare chip by inputting a signal from an external apparatus to the bare chip is electrically connected, the at least two or more groups of external connection terminals being formed outside an image area of the bare chip, wherein at least one group of terminals constitutes a first group of terminals, another group of terminals constitutes a second group of terminals, the first group of terminals doubles as the second group of terminals, and a substrate for inspection doubling as a substrate for mounting is electrically connected to the first group of terminals.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 22, 2012
    Applicant: OLYMPUS MEDICAL SYSTEMS CORP.
    Inventors: Kazuhisa HOSHI, Jun HIROYA, Seiji IWASAKI, Akira MURAMATSU, Yuichi WATAYA, Toru KUCHIMARU, Hiroshi ISHII, Tomoaki YAMASHITA
  • Publication number: 20120018872
    Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Inventors: Mudasir Ahmad, Kuo-Chuan Liu, Mohan Nagar, Bangalore Shanker
  • Publication number: 20110309486
    Abstract: A method of forming a capped die forms a cap wafer having a top side and a bottom side. The bottom side is formed with 1) a plurality of device cavities having a first depth, and 2) a plurality of second cavities that each have a greater depth than the first depth. At least some of the plurality of second cavities each generally circumscribe at least one of the device cavities. The method then secures the cap wafer to a device wafer in a manner that causes a plurality of the device cavities each to circumscribe at least one of circuitry and structure on the device wafer. Next, the method removes at least a portion of the top side of the cap wafer to expose the second cavities. This forms a plurality of caps that each protect the noted circuitry and structure.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 22, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventors: Mitul Dalal, Li Chen
  • Publication number: 20110304034
    Abstract: A semiconductor wafer bonding product according to the present invention includes: a semiconductor wafer; a transparent substrate provided at a side of a functional surface of the semiconductor wafer; a spacer provided between the semiconductor wafer and the transparent substrate; and a bonded portion continuously provided along a periphery of the semiconductor wafer, the transparent substrate being bonded to the semiconductor wafer through the bonded portion. It is preferred that a minimum width of the bonded portion is 50 ?m or more.
    Type: Application
    Filed: February 15, 2010
    Publication date: December 15, 2011
    Inventors: Hirohisa Dejima, Masakazu Kawata, Masahiro Yoneyama, Toyosei Takahashi, Fumihiro Shiraishi, Toshihiro Sato
  • Patent number: 8076771
    Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Ando
  • Publication number: 20110285003
    Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 24, 2011
    Applicant: Panasonic Corporation
    Inventors: KIYOKAZU ITOI, TOSHIYUKI FUKUDA, YOSHIKI TAKAYAMA, TETSUSHI NISHIO, TETSUMASA MARUO
  • Patent number: 8049311
    Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Chee Chian Lim, Yoke Chin Goh, Koh Hoo Goh, May Ting Hng
  • Patent number: 8044429
    Abstract: A light-emitting device including a light-emitting element and a substrate where the light-emitting element is arranged. A housing part housing the light-emitting element and having a shape that is tapered upward from the substrate and a metal frame surrounding the light-emitting element and including the side face of the housing part made into an almost mirror-polished surface are provided on the substrate.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 25, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Masahiro Sunohara, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama, Naoyuki Koizumi, Hideaki Sakaguchi
  • Publication number: 20110254136
    Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: Panaconic Corporation
    Inventors: Makoto TSUTSUE, Masaki Utsumi
  • Patent number: 8035209
    Abstract: A micromechanical device having a substrate wafer has at least one first cavity and one second cavity, the cavities being hermetically separated from each other, the first cavity having a different internal atmospheric pressure than the second cavity. The cavities are capped by a thin film cap. A method is for manufacturing a micromechanical device which has a thin film cap having cavities of different internal atmospheric pressures.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 11, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Julian Gonska, Ralf Hausner
  • Publication number: 20110221042
    Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lisa H. Karlin, Lianjun Liu, Alex P. Pamatat, Paul M. Winebarger
  • Patent number: 8018030
    Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Publication number: 20110215429
    Abstract: An electronic device package manufacturing method includes: forming a metal film on both surfaces of the cover substrate so that the metal film on one surface and the metal surface on the other surface conduct with each other; aligning and superimposing the cover substrate and the base substrate; and bonding the base substrate and the cover substrate together via the metal film by anodic bonding by bringing a negative electrode plate into contact with the base substrate on an entire surface opposite to a surface bonded to the cover substrate, bringing a positive electrode plate into contact with the cover substrate on an entire surface opposite to a surface bonded to the base substrate, and applying a voltage between the positive and negative electrode plates. The base substrate and the cover substrates can be thus bonded together via the metal film by anodic bonding in a stable manner.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 8, 2011
    Inventor: Yoshifumi Yoshida
  • Publication number: 20110215459
    Abstract: An interconnect includes an elastic body, an electric conductor and a spacer. The elastic body has a first surface, a second surface, a first hole extending from the first surface to the second surface, and a second hole extending from the first surface to the second surface. The electric conductor is disposed in the first hole of the insulating body for contacting one of a plurality of balls of the first integrated circuit package and one of a plurality of conductor pads of the second integrated circuit package. The electric conductor includes an elastic body and electric conductor particles disbursed in the elastic body. The spacer is disposed in the second hole.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 8, 2011
    Inventors: Jesus S. Sangalang, Kazuya Takahashi
  • Patent number: 8004053
    Abstract: A micromechanical device according to an aspect of the present invention includes, a substrate, a micromachine which is mounted on the substrate, is provided with a mechanism deformed by a function of an electric field, and changes the electrical characteristics concomitantly with the deformation, an inner inorganic sealing film which contains an inorganic material, is provided on a principal surface of the substrate, covers the micromachine through a hollow section containing a gaseous body therein, and is provided with opening shape sections allowing the hollow section to communicate with the outside, an organic sealing film which contains an organic material, is formed on the inner inorganic sealing film, and blocks up the opening shape sections, and an outer inorganic sealing film which contains an inorganic material with lower moisture permeability than the organic material, is formed on the organic sealing film, and covers the organic sealing film.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Miyagi, Michinobu Inoue, Susumu Obata, Yoshiaki Sugizaki
  • Patent number: 7994617
    Abstract: An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuyuki Arai, Yuko Tachimura, Yohei Kanno, Mai Akiba
  • Publication number: 20110186983
    Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.
    Type: Application
    Filed: December 27, 2010
    Publication date: August 4, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi HASEGAWA
  • Patent number: 7990025
    Abstract: A hermetic package for electronic components which is made of metallic silicon is disclosed. The package includes a plurality of silicon elements which are bonded together. In the first embodiment, a cavity is hollowed out in the cover to house the Application Specific Integrated Circuit oscillator and the resonator. In a second embodiment, the cavity is formed in the base member with a plurality of pedestal shelves to hold the resonator above and out of contact with the electrical circuitry for the oscillator and thermal controls.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: August 2, 2011
    Inventors: Pablo Ferreiro, Kenneth Martin, John Cline
  • Publication number: 20110180924
    Abstract: A MEMS module package includes a carrier, a lid capped on the carrier, a spacer disposed between the carrier and the lid, and a chip mounted on the spacer and electrically connected with the carrier. The spacer has a channel in communication between a chamber and a receiving hole of the lid, and the chip is received in the chamber of the lid and corresponding to the channel of the spacer. Therefore, an external signal can be transmitted from the receiving hole of the lid into the chamber of the lid through the channel of the spacer so as be received by the chip.
    Type: Application
    Filed: February 18, 2010
    Publication date: July 28, 2011
    Applicant: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Jyong-Yue TIAN, Jen-Chuan Yeh
  • Publication number: 20110169154
    Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Young Do Kweon, J. Michael Brooks, Tongbi Jiang
  • Patent number: 7977786
    Abstract: An improved MEMS device and method of making. Channels are formed in a first substrate around a plurality of MEMS device areas previously formed on the first substrate. Then, a plurality of seal rings are applied around the plurality of MEMS device areas and over at least a portion of the formed channels. A second substrate is attached to the first substrate, then the seal ring surrounded MEMS device areas are separated from each other. The channels include first and second cross-sectional areas. The first cross-sectional area is sized to keep saw debris particles from entering the MEMS device area.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: July 12, 2011
    Assignee: Honeywell International Inc.
    Inventors: Jeff A. Ridley, Max Glenn, James C. Nohava, Robert D. Horning, Jane Rekstad
  • Publication number: 20110163438
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Noriyuki TAKAHASHI, Mamoru SHISHIDO
  • Publication number: 20110140260
    Abstract: A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: SIERRA MONOLITHICS, INC.
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Patent number: 7960215
    Abstract: An electronic device includes: a base; a conductor pattern formed on the base; and a circuit chip electrically connected to the conductor pattern. The electronic device further includes a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes layers stacked in the thickness direction of the base. The lowermost layer of the layers is closest to the base and softer than the layer that is at least one of the remaining layers. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kobayashi, Kenji Kobae, Shuichi Takeuchi, Hidehiko Kira
  • Patent number: 7956347
    Abstract: A novel package that integrates components for a modulating retro reflector into a single package is disclosed according to various embodiments. According to some embodiments the package is configured to secure a retro reflector, a quantum well modulator and photodiode. In some embodiments, the package may include interconnects to surface mount to a circuit board. Such interconnects may be coupled with the photodiode and/or the quantum well modulator. In some embodiments, the package may be constructed of liquid crystal polymers and/or may include one or more windows.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Cubic Corporation
    Inventors: Mahyar Dadkhah, Tony Maryfield, Thomas Davidson
  • Publication number: 20110068462
    Abstract: A structure. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
    Type: Application
    Filed: November 24, 2010
    Publication date: March 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Peter Karidis, Mark Delorman Schultz
  • Patent number: 7898093
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: March 1, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 7884467
    Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 8, 2011
    Assignee: Lingsen Precision Industries, Ltd.
    Inventors: Chin-Ching Huang, Jiung-Yue Tien, Hsi-Chen Yang
  • Publication number: 20110012251
    Abstract: According to one embodiment, a semiconductor device includes a base substrate, at least one semiconductor chip provided above the base substrate, and a resin case covering the semiconductor chip and supported by the base substrate. A partition plate holds back extension of a crack occurring in the resin case being provided in the resin case.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi TERAMAE
  • Publication number: 20100308451
    Abstract: There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 9, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kotaro Kodani
  • Patent number: 7842552
    Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Peter Karidis, Mark Delorman Schultz