Stacked Arrangements Of Devices (epo) Patents (Class 257/E25.013)
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Patent number: 12224245Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die.Type: GrantFiled: December 23, 2019Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Sanka Ganesan, Robert L. Sankman, Sri Chaitra Jyotsna Chavali
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Patent number: 12087746Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.Type: GrantFiled: March 30, 2023Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Chong Zhang, Cheng Xu, Junnan Zhao, Ying Wang, Meizi Jiao
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Patent number: 12057379Abstract: A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.Type: GrantFiled: March 24, 2022Date of Patent: August 6, 2024Assignee: CISCO TECHNOLOGY, INC.Inventors: D. Brice Achkir, Shobhana Ram Punjabi, Jie Xue
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Patent number: 12028597Abstract: An image pickup apparatus includes a stacked device in which a plurality of semiconductor devices respectively including a plurality of through electrodes are stacked, a first semiconductor device, among the plurality of semiconductor devices, in which thermal resistance of a through electrode is highest among the plurality of through electrodes, is disposed in front of a first surface on which a first circuit that is one of the semiconductor circuits having a largest heat generation amount is formed, the plurality of through electrodes of the first semiconductor device are conformal vias, and the plurality of through electrodes of semiconductor devices other than the first semiconductor device are filled vias.Type: GrantFiled: July 20, 2022Date of Patent: July 2, 2024Assignee: OLYMPUS CORPORATIONInventors: Takuro Suyama, Ken Yamamoto, Takatoshi Igarashi
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Patent number: 11942455Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.Type: GrantFiled: May 11, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Yeongbeom Ko, Youngik Kwon, Jong Sik Paek, Jungbae Lee
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Patent number: 11848293Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.Type: GrantFiled: July 15, 2021Date of Patent: December 19, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sunkyoung Seo, Teak Hoon Lee, Chajea Jo
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Patent number: 11804441Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate including a first metal layer and a second metal layer; a cavity in the substrate, wherein a portion of the first metal layer in the substrate and a portion of the second metal layer in the substrate are exposed in the cavity; and a bridge component in the cavity, the bridge component includes a first conductive contact at a first face and a second conductive contacts at an opposing second face, wherein the second face of the bridge component is between the first face of the bridge component and a bottom surface of the cavity in the substrate, and wherein the second conductive contact is electrically coupled to the portion of the first metal layer in the cavity.Type: GrantFiled: June 16, 2020Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Debendra Mallik
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Patent number: 11791316Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.Type: GrantFiled: November 8, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Travis M. Jensen, David R. Hembree
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Patent number: 11742294Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.Type: GrantFiled: May 3, 2021Date of Patent: August 29, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jongho Park, Seunghwan Kim, Junyoung Oh, Yonghyun Kim, Yongkwan Lee, Junga Lee
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Patent number: 11676925Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 ?m to 100 ?m, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.Type: GrantFiled: October 13, 2021Date of Patent: June 13, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jiseok Hong, Hyuekjae Lee, Jongpa Hong, Jihwan Hwang, Taehun Kim
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Patent number: 11664318Abstract: An apparatus including a carrier mount having a staircase of steps in an opening in the carrier mount and a plurality of dies, each one of the dies having at least a portion of an edge of a major surface thereof located on one of the steps corresponding to the one of the dies such that the dies form a stack, major surfaces of the dies being substantially parallel in the stack, each of the dies having one or more electro-optical devices thereon.Type: GrantFiled: December 31, 2020Date of Patent: May 30, 2023Assignee: Nokia Solutions and Networks OyInventor: Argishti Melikyan
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Patent number: 11423950Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.Type: GrantFiled: May 28, 2020Date of Patent: August 23, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Woon Park, Jae-Sang Yun
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Patent number: 11239821Abstract: An electronic component device includes first and second mount boards, and first, second, and third electronic components. The first electronic component includes a first major surface and a second major surface, and is disposed on the first mount board. The first major surface is positioned closer to the first mount board than the second major surface. The second electronic component includes a third major surface and a fourth major surface, and is disposed on the second mount board. The third major surface is positioned closer to the second mount board than the fourth major surface. The third electronic component includes a fifth major surface and a sixth major surface, and is disposed on the second mount board. The fifth major surface is positioned closer to the second mount board than the sixth major surface. The second major surface directly contacts the fourth and sixth major surfaces, or indirectly contacts the fourth and sixth major surfaces with a bonding layer interposed therebetween.Type: GrantFiled: December 5, 2019Date of Patent: February 1, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Masato Nomiya
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Patent number: 11043805Abstract: A semiconductor device includes an internal circuit in a core region, a first protection circuit in a peripheral region surrounding the core region, the first protection circuit including first and second protection sections and a first fuse, and a first pad receiving a first signal. The first pad is electrically connected to the first protection section via the first fuse, and the first pad is electrically connected to the second protection section. The internal circuit is electrically connected to the first pad through the second protection section. When a surge voltage having a magnitude equal to or larger than a predetermined voltage is input to the first pad, each of the first and second protection sections prevent the surge voltage from being applied into the internal circuit.Type: GrantFiled: February 4, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Jang Hoo Kim
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Patent number: 10878148Abstract: A variable signal flow control method for realizing chip reuse and a communication terminal for realizing chip reuse using the variable signal flow control method, the method comprises the following steps: using at least two identical integrated circuit (IC) chips, the respective IC chips achieving different flows of the control signals according to different logic control signals; controlling the logic control signals such that the respective IC chips achieves the flow of the corresponding control signals. The method can achieve control function of different signal flows for two identical IC chips, thereby greatly simplifying chip types for achieving IC system functions, greatly reducing development costs of the IC system and management complexity of the mass production supply chain.Type: GrantFiled: June 30, 2017Date of Patent: December 29, 2020Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.Inventor: Sheng Lin
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Patent number: 10354978Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.Type: GrantFiled: January 10, 2018Date of Patent: July 16, 2019Assignee: POWERTECH TECHNOLOGY INC.Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
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Patent number: 9971549Abstract: In a method of operating a memory device, a first write command, a first write address, and first write data are received by a first memory device through a channel. The first write command, received by the first memory device, is sensed by a controller. The controller is connected to the channel and controls a second memory device. The first memory device and the second memory device are different types of memory devices. When the first write command is sensed by the controller, a first write log is generated using the first write address and the first write data. The first write log is stored into a buffer.Type: GrantFiled: April 19, 2017Date of Patent: May 15, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo-Hwan Oh, Yong-Jun Yu, In-Su Choi
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Patent number: 9041179Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: GrantFiled: March 6, 2014Date of Patent: May 26, 2015Assignee: SONY CORPORATIONInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 9029199Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.Type: GrantFiled: June 21, 2013Date of Patent: May 12, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Shinichi Sakurada
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Patent number: 9029989Abstract: A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.Type: GrantFiled: August 16, 2013Date of Patent: May 12, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Soojeoung Park
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Patent number: 9030004Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.Type: GrantFiled: October 24, 2012Date of Patent: May 12, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Tae Park, Kang-Wook Lee, Young-Don Choi, Yun-Sang Lee
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Patent number: 9024452Abstract: A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.Type: GrantFiled: May 24, 2012Date of Patent: May 5, 2015Assignee: STS Semiconductor & Telecommunications Co., Ltd.Inventor: Jung Hwan Chun
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Patent number: 9024403Abstract: An image sensor package and image sensor chip capable of being slenderized while enhancing the reliability with respect to physical impact are provided. The image sensor package includes an image sensor chip provided with a pixel domain at a central portion of an upper surface thereof, a substrate disposed at an upper side of the image sensor chip so as to be flip-chip bonded with respect to the image sensor chip, provided with a hole formed at a position corresponding to the pixel domain, and formed of organic material, a printed circuit board at which the substrate provided with the image sensor chip bonded thereto is mounted, and a solder ball configured to electrically connect the substrate to the printed circuit board.Type: GrantFiled: April 25, 2013Date of Patent: May 5, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Sang Park, Hyo Young Shin
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Patent number: 9024423Abstract: A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.Type: GrantFiled: April 26, 2010Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Akira Muto, Yuichi Machida, Nobuya Koike, Atsushi Fujiki, Masaki Tamura
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Patent number: 9000575Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.Type: GrantFiled: February 23, 2012Date of Patent: April 7, 2015Assignee: Seiko Epson CorporationInventor: Hideo Imai
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Patent number: 8975752Abstract: A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.Type: GrantFiled: January 9, 2008Date of Patent: March 10, 2015Assignee: Oracle America, Inc.Inventors: Alex Chow, R. David Hopkins, Robert J. Drost
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Patent number: 8970023Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.Type: GrantFiled: February 4, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bruce C. S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
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Patent number: 8951840Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.Type: GrantFiled: December 4, 2012Date of Patent: February 10, 2015Assignee: Beijing University of TechnologyInventors: Fei Qin, Guofeng Xia, Tong An, Chengyan Liu, Wei Wu, Wenhui Zhu
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Patent number: 8952517Abstract: Provided are a package-on-package device and a method of fabricating the same. In the device, solder balls may be disposed on two opposing side regions of a package substrate, such that the device can have a reduced size or width. In addition, input/output pads of the logic chip and the solder balls, which need to be directly connected to each other, can be disposed adjacent to each other. As a result, it is possible to improve routability of signals to and from the solder balls and to reduce the lengths of the interconnection lines. Accordingly, it is possible to reduce any signal interference, to increase signal delivery speed, and to improve signal-quality and power-delivery properties.Type: GrantFiled: March 14, 2013Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Heungkyu Kwon, JeongOh Ha
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Patent number: 8941233Abstract: Integrated circuit (IC) packages with an inter-die thermal spreader are disclosed. A disclosed IC package includes a plurality of stacked dies disposed on a package substrate. A heat spreader is disposed on a top die of the plurality of stacked dies. The IC package further includes a thermal spreader layer disposed adjacent to at least one die of the plurality of stacked dies. The thermal spreader layer may extend out of a periphery of the plurality of stacked dies and may be attached to the heat spreader through a support member.Type: GrantFiled: February 22, 2012Date of Patent: January 27, 2015Assignee: Altera CorporationInventors: Tony Ngai, Arifur Rahman
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Patent number: 8941230Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.Type: GrantFiled: August 26, 2013Date of Patent: January 27, 2015Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Kyozuka, Akihiko Tateiwa, Yuji Kunimoto, Jun Furuichi
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Patent number: 8941247Abstract: In a packaging structure for a microelectromechanical-system (MEMS) resonator system, a resonator-control chip is mounted on a lead frame having a plurality of electrical leads, including electrically coupling a first contact on a first surface of the resonator-control chip to a mounting surface of a first electrical lead of the plurality of electrical leads through a first electrically conductive bump. A MEMS resonator chip is mounted to the first surface of the resonator-control chip, including electrically coupling a contact on a first surface of the MEMS resonator chip to a second contact on the first surface of the resonator-control chip through a second electrically conductive bump. The MEMS resonator chip, resonator-control chip and mounting surface of the first electrical lead are enclosed within a package enclosure that exposes a contact surface of the first electrical lead at an external surface of the packaging structure.Type: GrantFiled: February 27, 2014Date of Patent: January 27, 2015Assignee: SiTime CorporationInventors: Pavan Gupta, Aaron Partridge, Markus Lutz
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Patent number: 8921159Abstract: A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening.Type: GrantFiled: June 21, 2013Date of Patent: December 30, 2014Assignee: Linear Technology CorporationInventor: David Alan Pruitt
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Patent number: 8916956Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: GrantFiled: December 2, 2013Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Patent number: 8907500Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.Type: GrantFiled: February 4, 2013Date of Patent: December 9, 2014Assignee: Invensas CorporationInventors: Belgacem Haba, Wael Zohni
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Patent number: 8896112Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.Type: GrantFiled: March 15, 2013Date of Patent: November 25, 2014Assignee: Oracle International CorporationInventors: Hiren D. Thacker, Ashok V. Krishnamoorthy, John E. Cunningham, Chaoqi Zhang
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Patent number: 8890330Abstract: Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire.Type: GrantFiled: November 30, 2012Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Man Kim, In-Ku Kang, Ji-Hyun Lee
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Patent number: 8884412Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: GrantFiled: December 2, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Patent number: 8841776Abstract: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.Type: GrantFiled: February 25, 2008Date of Patent: September 23, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 8836146Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.Type: GrantFiled: March 2, 2007Date of Patent: September 16, 2014Assignee: Qualcomm IncorporatedInventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
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Patent number: 8836101Abstract: Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.Type: GrantFiled: September 24, 2010Date of Patent: September 16, 2014Assignee: Infineon Technologies AGInventors: Chooi Mei Chong, Teck Sim Lee
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Patent number: 8822281Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.Type: GrantFiled: February 23, 2010Date of Patent: September 2, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Yaojian Lin, Seung Uk Yoon
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Patent number: 8823159Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.Type: GrantFiled: July 2, 2013Date of Patent: September 2, 2014Assignee: Micron Technology, Inc.Inventors: Seng Kim Dalson Ye, Chin Hui Chong, Choon Kuan Lee, Wang Lai Lee, Roslan Bin Said
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Patent number: 8816489Abstract: Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.Type: GrantFiled: May 14, 2012Date of Patent: August 26, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Krishna K. Parat
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Patent number: 8796861Abstract: Semiconductor packages including a substrate, a plurality of first semiconductor chips stacked on the substrate, a second semiconductor chip interposed between the substrate and a lowermost semiconductor chip among the first semiconductor chips, and a supporting member disposed between the substrate and the lowermost semiconductor chip among the first semiconductor chips to support the first semiconductor chips, may be provided. The supporting member may include a passive element such as a capacitor, a resistor, or an inductor. By including the supporting member, the semiconductor packages may achieve a smaller planar size and have an improved tolerance for subsequent interconnections.Type: GrantFiled: September 4, 2012Date of Patent: August 5, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-jin Kim, Jong-keun Ahn, Sun-Pil Youn
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Patent number: 8796822Abstract: A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.Type: GrantFiled: October 7, 2011Date of Patent: August 5, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
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Patent number: 8791558Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.Type: GrantFiled: December 29, 2010Date of Patent: July 29, 2014Assignee: SK Hynix Inc.Inventors: Jin Ho Bae, Ki Young Kim, Jong Hyun Nam
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Patent number: 8779433Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.Type: GrantFiled: May 25, 2011Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Yoshinori Ieda, Kiyoshi Kato, Yuto Yakubo, Yuki Hata
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Patent number: 8779570Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.Type: GrantFiled: March 19, 2008Date of Patent: July 15, 2014Assignee: STATS ChipPAC Ltd.Inventors: Seong Bo Shim, TaeWoo Kang, Yong Hee Kang
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Patent number: 8772915Abstract: According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.Type: GrantFiled: June 30, 2011Date of Patent: July 8, 2014Assignee: Broadcom CorporationInventors: Tarek Kaylani, Zhihui Wang, Kenneth Kindsfater, Balasubramanian Annamalai, Jeff Echtenkamp