Abstract: A power semiconductor module includes a plurality of power semiconductor chips. A housing accommodates the power semiconductor chips. A first module electrode on a first side of the housing electrically is connected to a first chip electrode of the power semiconductor chips. A second module electrode on a second side of the housing electrically is connected to a second chip electrode. A surge arrester arrangement with a surge arrester is accommodated in the housing such that a first electrode of the surge arrester arrangement is provided at the first side of the housing and a second electrode of the surge arrester arrangement is provided at the second side of the housing. The power semiconductor chips are arranged in an annular region in the housing and the surge arrester arrangement is arranged within the annular region.

Abstract: A brush apparatus for a slip ring system of a current-energized electric machine for a motor vehicle is provided for supplying a rotor of the electric machine with current, wherein the brush apparatus is securable to a component of the electric machine that is mounted in fixed relation to the rotor. The brush apparatus includes a brush carrier having a cartridge-type holder and a brush arranged in the cartridge-type holder and forming a sliding contact with a slip ring of the slip ring system. The brush apparatus also includes a retaining device, formed from an electrically insulating material for retaining the brush carrier, which has a securing region for securing the brush apparatus on the component, and a heat-conducting core enclosed in the retaining device, which is exposed for the purpose of heat dissipation at least in the securing region of the retaining device that is couplable to the component.

Abstract: A power tool includes a brushless DC motor having a stator and a rotor pivotably arranged inside the stator, the stator including a first winding, a second winding, and a third winding. Each winding is arranged at at least two opposite poles connected together. The stator windings may be connected in a delta configuration by electrically coupling adjacent terminals of the first and second windings, second and third windings, and third and first windings at three connection points. A baffle may be provided in parallel and adjacent to the stator, the baffle including at least one conductive routing or stamping to facilitate electrically coupling the first, second, and third windings in at least one of a delta or a wye configuration.

Abstract: An architecture of interconnected electronic power modules for a polyphase rotary machine, includes electrically interconnected power modules (5) and a connector (6) including one or more layers formed by pluralities of conductive traces borne by plates, such as to connect the power modules (51 to 53) to one another and to electrical elements of the rotary machine. The power modules (51 to 53) include a plurality of connection elements (510 to 530) brazed directly to components of the power modules (51 to 53) and, in the upper part, to conductive traces of the connector (6). This architecture includes a heat sink (4) equipped with open cavities (41 to 43) for receiving the power modules (51 to 53). A polyphase rotary machine is also provided using such an architecture, in particular a dual three-phase alternator with synchronous rectification.

Abstract: Provided is a rotating electric machine capable of preventing an outer race of a bearing from rotating because of a reduction in force for coupling a bearing housing portion and the outer race of the bearing. A resin case (24) uses thermal expansion to fill a clearance between the bearing housing portion and the outer race of a counter-driving side bearing. A hook (25) projecting inward in a radial direction is formed at least at one position on a circumferential edge portion of the resin case (24) on a side opposite to a rotor. The bearing housing portion includes a concave portion to which the hook (25) is to be locked, which is formed on a flange portion inside of which a shaft passes.

Abstract: A wiring unit (U) for automatic transmission mounted in an automatic transmission of an automotive vehicle and configured to execute a control relating to a speed changing operation includes a wiring harness (WH), a ROM (1) connected to the wiring harness and a holding plate (2) made of metal for holding these. The holding plate (2) is formed with a holding portion (33) on which the ROM (1) is to be placed, and the holding portion (33) is integrally formed with a plurality of swaging pieces (36) for fixing the ROM (1) on the holding portion (33) by being swaged to the ROM (1). Further, the ROM (1) is formed with a positioning protrusion (37), and the holding portion (33) is formed with a receiving hole (39) into which the positioning protrusion (37) is aligned and fitted.

Abstract: A method of cooling electronics of an alternator includes mounting the electronics onto an electrically conductive electronics chassis, and electrically connecting the electronics chassis to a positive DC (B+) output voltage terminal of the alternator, whereby the electronics chassis is electrically insulated from ground potential and thermally conductively isolated from the alternator housing. An alternator includes the housing at ground potential, the electronics chassis at B+ potential, and the mounted electronics. The electronics chassis is electrically insulated and conductively isolated from the housing. An electric machine includes the electronics chassis having an electronics mounting surface, and a convection surface, and defines an electrical bus for conducting a B+ potential. An electronics chassis assembly has an insulator secured between the housing at ground potential and the electronics chassis.

Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.

Abstract: There is provided a system and method for an externally wire bondable chip scale package in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad disposed thereon, a packaged device attached to the substrate, wherein an electrode of the packaged device is wirebonded to the first contact pad, and an unpackaged device, wherein an electrode of the unpackaged device is coupled to the substrate. By flipping the packaged device within the module and utilizing wire bondable finishes on the packaged device, an externally wire bondable chip scale package may be provided. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, a single assembly line, facilitated die substitution, reduced heat stress, higher package density, and a simplified single package structure for reduced fabrication time and cost.

Abstract: A light output device comprises a substrate arrangement comprising a plurality of light source circuits integrated into the structure of the substrate arrangement. Each light source circuit comprises a light source device arrangement (4) having two terminals and a transistor circuit (7). Each light source circuit is supplied with power from an associated pair the power connections (10,11,14,15,20), and at least two light source circuits (4,7) share the same pair of power connections. A set of control connections (18) are provided for receiving external control signals for controlling the transistor circuits (7). A set of non-overlapping electrodes (10,11,14,15,18,20) provide the internal connections between the power connections, the light source device terminals and the transistor circuits, and each light source device is individually independently controllable.

Abstract: A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips.

Abstract: This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.

Abstract: An arrangement comprising at least one power semiconductor module and a transport packaging, wherein the power semiconductor module has a base element, a housing and connection elements and the transport packaging has a generally planar cover layer, a cover film and at least one trough-like plastic shaped body for each power semiconductor module. The at least one plastic shaped body only partly encloses the respective power semiconductor module and a part of the plastic shaped body does not directly contact the power semiconductor module. Furthermore, a first side of the at least one power semiconductor module becomes situated directly or indirectly on the first main surface of the cover layer, while the cover film covers the further sides of the power semiconductor module directly and/or indirectly, and bears at least partly against the plastic shaped body.

Abstract: A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board.

Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.

Abstract: Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; stacking a second device over a first device between the first lead-finger system and the second lead-finger system; connecting the second device to the second lead-finger system with a bump bond; stacking a dummy device over the second device; and connecting the first device to the first lead-finger system with a wire bond.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; stacking a first device over the support structure; stacking a second device over the first device; connecting the first device and the second device to the lead-finger system; stacking a dummy device over the second device; and exposing a support structure bottom side and a dummy device top side for thermal dissipation.

Abstract: Disclosed is a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted. In manufacturing plural semiconductor devices for providing different amounts of output current, arrangements and numbers of leads to which semiconductor chips for power transistors of the semiconductor devices are to be electrically connected are changed according to output current requirements for the semiconductor devices, whereas arrangements and numbers of leads to which semiconductor chips for control circuits of the semiconductor devices are to be electrically connected are fixed to be common to the semiconductor devices. In this way, the probability of malfunction of control circuits (PWM circuits) of the semiconductor devices can be reduced, so that a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted can be provided.

Abstract: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.

Abstract: Monolithic semiconductor structures having at least two pairs of two lateral semiconductor devices combined on a first surface of a single semiconductor substrate. Embodiments include connected source terminals defining common source terminals.

Abstract: An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

Abstract: A semiconductor module has a coupling substrate which is used for the internal electrical coupling of an integrated circuit on adjacent semiconductor chips. The semiconductor chips have integrated circuits and are arranged on a mount structure. The semiconductor chips are externally connected to external contacts. The coupling substrate overlaps edge areas of the adjacent semiconductor chips.