Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.

Abstract: Graphene semiconductor device, a method of manufacturing a graphene semiconductor device, an organic light emitting display and a memory, include forming a multilayered member including a sacrificial substrate, a sacrificial layer, and a semiconductor layer deposited in sequence, forming a transfer substrate on the semiconductor layer, forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sacrificial substrate from the semiconductor layer, forming a second laminate by forming a graphene layer on a base substrate, combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer, and removing the transfer substrate.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Abstract: A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A gate electrode is formed on a first conductivity type substrate. A second conductivity type implantation region is formed in the first conductivity type substrate. A first conductivity type implantation region is formed by implanting the first conductivity type impurities into the first conductivity type substrate to a depth deeper than the second conductivity type implantation region. An ISSG oxide film whose thickness ranges from 60 nm to 100 nm is formed to cover the first conductivity type substrate and the gate electrode. A silicone nitride film is formed on the ISSG oxide film. A second silicone oxide film is formed on the silicon nitride film. A sidewall is formed to cover the gate electrode and the first conductivity type substrate. A source/drain diffusion layer is formed by implanting second conductivity type impurities into the first conductivity type substrate.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The contact plugs are preferably formed in a different process step than the interconnects.