Storage Electrode Having Multiple Wings (epo) Patents (Class 257/E27.089)
  • Patent number: 11508720
    Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 22, 2022
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 10497602
    Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, Gordon M. Grivna
  • Patent number: 10453764
    Abstract: The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-An Chen, Po-Wei Lu, Ming Tsung Shen, Yu-Tzu Peng
  • Patent number: 10163495
    Abstract: A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9786670
    Abstract: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 8932933
    Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ian C. Laboriante, Prashant Raghu
  • Patent number: 8884350
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 8766343
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Patent number: 8686446
    Abstract: A capacitor device prevents capacitor failure and pixel failure by preventing the capacitor from experiencing a short circuit caused by disconnection of a bridge formed between electrodes of the capacitor and a display apparatus having the capacitor device. A display device comprises a thin film transistor, a light emitting device, and the capacitor device described above.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sang-Min Hong
  • Patent number: 8471321
    Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
  • Patent number: 8405089
    Abstract: To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Uchiyama
  • Patent number: 8405216
    Abstract: The present invention discloses an interconnect structure for an integrated circuit formed on a semiconductor substrate. In one embodiment, the first conductive layer is formed above the semiconductor substrate. A first via contact is formed on the first conductive layer. A second via contact is formed on the first via contact. A second conductive layer is formed on the second via contact. One of the first and second via contacts has a cross-sectional area substantially larger that of another for improving a landing margin thereof, thereby eliminating a need of using a landing pad between the first and second via contacts.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8384143
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Patent number: 8283750
    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: October 9, 2012
    Assignee: IPDIA
    Inventors: Lionel Guiraud, Francois Lecornec, Johan H. Klootwijk, Freddy Roozeboom, David D. R. Chevrie
  • Patent number: 8169015
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 1, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Patent number: 8124491
    Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
  • Patent number: 8119476
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Patent number: 7994561
    Abstract: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 9, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hun Kim, Byung Soo Eun
  • Patent number: 7932550
    Abstract: An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external surface by an etch process that resists destructive collapse of the conductive structure.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: April 26, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Torek, Kevin Shea, Thomas Graettinger
  • Patent number: 7902584
    Abstract: This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of a opening penetrating through the semiconductor layer; a first gate electrode penetrating through the opening and isolated from the semiconductor layer by the first gate dielectric film; a second gate dielectric film formed on a side surface and an upper surface of the semiconductor layer located on the first gate electrode; and a second gate electrode provided on the side surface and the upper surface of the semiconductor layer via the second gate dielectric film, isolated from the first gate electrode, and superimposed on the first gate electrode.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroomi Nakajima
  • Patent number: 7888724
    Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
  • Patent number: 7838919
    Abstract: The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Kiyomi Okamoto, Tetsurou Sugioka, Kazuki Adachi
  • Patent number: 7795648
    Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: September 14, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
  • Patent number: 7781298
    Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 24, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
  • Patent number: 7768055
    Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
  • Patent number: 7745868
    Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: June 29, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Masahiko Ohuchi
  • Patent number: 7709367
    Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Jung Lee, Ik-Soo Choi, Chang-Youn Hwang, Mi-Hyune You
  • Patent number: 7700430
    Abstract: A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage from the data line. The unit cell further includes a phase change material for changing phase depending on heat generated by the voltage and a top electrode, connected to a substantially ground voltage.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Guil Yang, Hong-Sik Jeong, Young-Nam Hwang
  • Patent number: 7696567
    Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: April 13, 2010
    Assignee: Micron Technology, Inc
    Inventors: Gordon Haller, Sanh Dang Tang, Steve Cummings
  • Patent number: 7667257
    Abstract: Method for solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, and having difficulty in electrical by connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first and second upper electrodes. The conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing a tantalum oxide film formed on a titanium nitride film, which is brought to a completely conducting state when heat treated. A crown structure is formed without removing the insulating film, in which a trench has been formed, by wet etching, whereby a stacked trench capacitor, which has double the capacity is provided while eliminating the collapse of the lower electrode or pair bit defect.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: February 23, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shinpei Iijima
  • Patent number: 7638401
    Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Toshiyuki Nagata
  • Patent number: 7544985
    Abstract: In one embodiment, a semiconductor device comprises a base and a tapered wall formed on the base. The wall has a midline and also has an inner sidewall and an outer sidewall. The inner sidewall and the outer sidewall are substantially symmetrical with each other in relation to the midline. Thus, the reliability of the semiconductor capacitor structure can be improved and the throughput can be increased. Also, further scaling down of semiconductor devices can be facilitated with the principles of the present invention.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: June 9, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Gwan Shim, Chang-Ki Hong, Sang-Jun Choi, Jeong-Nam Han
  • Patent number: 7452769
    Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: November 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park
  • Patent number: 7449739
    Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: November 11, 2008
    Assignee: Infineon Technologies AG
    Inventors: Johannes Heitmann, Peter Moll, Odo Wunnicke, Till Schloesser
  • Patent number: 7442979
    Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R Shea
  • Patent number: 7413951
    Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: August 19, 2008
    Assignee: Qimonda AG
    Inventors: Stephan Kudelka, Peter Moll, Stefan Jakschik, Odo Wunnicke
  • Patent number: 7259414
    Abstract: This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: August 21, 2007
    Assignee: STMicroelectronics SA
    Inventors: Catherine Mallardeau, Pascale Mazoyer, Marc Piazza
  • Publication number: 20070170487
    Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 26, 2007
    Inventors: Johannes Heitmann, Peter Moll, Odo Wunnicke, Till Schloesser
  • Publication number: 20070170486
    Abstract: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.
    Type: Application
    Filed: May 24, 2006
    Publication date: July 26, 2007
    Inventor: Won-Mo PARK
  • Publication number: 20070108493
    Abstract: The present invention aims at solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, in particular, the problem of having difficulty in electrical connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first upper electrode and the second upper electrode. To solve the above problem, the conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing the characteristic of a tantalum oxide film formed on a titanium nitride film, which is brought to the completely conducting state when it is heat treated.
    Type: Application
    Filed: October 24, 2006
    Publication date: May 17, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Shinpei Iijima
  • Publication number: 20070029598
    Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.
    Type: Application
    Filed: April 5, 2006
    Publication date: February 8, 2007
    Inventor: Hiroyuki Uchiyama
  • Patent number: 7112840
    Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer and the size of the capacitor are factors for increasing parasitic capacitance and leakage currents. Also, the two capacitors are arranged diagonally, thereby widening the width of each capacitor formed. Furthermore, in case of forming the double capacitors according to the preferred embodiment of the present invention, an additional reticle is not required to form the contact holes for each capacitor due to their inverted disposition relationship.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: September 26, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seo-Min Kim, Cheol-Kyu Bok