Capacitor In Trench (epo) Patents (Class 257/E27.092)
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8921911
    Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Rexchip Electronics Corporation
    Inventors: Pin-Yuan Yu, Yi-Chun Shao, Chien-Hua Chu
  • Patent number: 8853762
    Abstract: A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Kuo-Cheng Chiang
  • Patent number: 8853048
    Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8766345
    Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Shu-Jen Han, George S. Tulevski
  • Patent number: 8753934
    Abstract: Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sivananda Kanakasabapathy, Hemanth Jagannathan, Geng Wang
  • Patent number: 8735957
    Abstract: Consistent with an example embodiment, there is a package that includes a first voltage terminal, and a second voltage terminal, a first die including a first MOSFET having a drain region electrically connected to the first voltage terminal and further having a source region, A second die is adjacent to the first die, the second die includes a second MOSFET having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal. The semiconductor package further includes a vertical capacitor having a first plate electrically connected to the drain region of the first MOSFET and a second plate electrically connected to the source region of the second MOSFET and the second plate is electrically insulated from the first plate by a dielectric material. The capacitor is integrated on the first die or the second die.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: May 27, 2014
    Assignee: NXP B.V.
    Inventor: Phil Rutter
  • Patent number: 8723243
    Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8637378
    Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
  • Patent number: 8624312
    Abstract: A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: January 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8624302
    Abstract: A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 7, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Matthew A. Ring, Henry G. Prosack, Jr.
  • Publication number: 20130328116
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8575670
    Abstract: A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8569816
    Abstract: A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8552414
    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hemantha Kumar Wickramasinghe, Kailash Gopalakrishnan
  • Patent number: 8552523
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: October 8, 2013
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 8547729
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: October 1, 2013
    Assignee: Nanya Technology Corporation
    Inventor: Wen-Kuei Huang
  • Patent number: 8525245
    Abstract: A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8502294
    Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Shyam Surthi, Lars Heineck
  • Patent number: 8482009
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
  • Publication number: 20130134491
    Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8441097
    Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Joseph M. Steigerwald, Nick Lindert, Steven J. Keating, Christopher J. Jezewski, Timothy E. Glassman
  • Patent number: 8415732
    Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
  • Patent number: 8410534
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8405135
    Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Fen Chen, Baozhen Li
  • Patent number: 8384140
    Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
  • Patent number: 8367497
    Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 5, 2013
    Assignee: Agere Systems LLC
    Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 8354675
    Abstract: A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Oh-jung Kwon, Junedong Lee, Chengwen Pei, Geng Wang
  • Patent number: 8350311
    Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kaneko, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
  • Patent number: 8324666
    Abstract: A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: JoBong Choi
  • Patent number: 8294189
    Abstract: A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Hou-Hong Chou, Chien-Sung Chu
  • Patent number: 8247305
    Abstract: A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Kuo-Chang Liao, Weijun Song, Dang Quan Liao
  • Patent number: 8227310
    Abstract: A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated cir
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Michael Sperling, Geng Wang
  • Patent number: 8193565
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 8193067
    Abstract: Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Herbert L. Ho, Edward J. Nowak
  • Patent number: 8164132
    Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 24, 2012
    Assignee: Round Rock Research, LLC
    Inventor: H. Montgomery Manning
  • Publication number: 20120091536
    Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Fang-Mei CHAO, Ming-I Chen, Ying-Ko Chin, Yi-Chiao Wang
  • Patent number: 8158485
    Abstract: An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 17, 2012
    Assignee: Qimonda AG
    Inventors: Daniel Köhler, Manfred Engelhardt, Peter Baars, Hans-Peter Sperlich
  • Patent number: 8129772
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8120103
    Abstract: A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Ro Hong
  • Patent number: 8110862
    Abstract: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert M. Rassel
  • Patent number: 8076722
    Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven Leibiger, Gary Dolny
  • Patent number: 8067793
    Abstract: A method for manufacturing a semiconductor device with high response speed and high reliability. In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Publication number: 20110272702
    Abstract: A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 10, 2011
    Applicant: International Business Machines Corporation
    Inventors: Oh-jung Kwon, Junedong Lee, Chengwen Pei, Geng Wang
  • Publication number: 20110215389
    Abstract: A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 8, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: JOBONG CHOI
  • Publication number: 20110193149
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 11, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
  • Patent number: 7989865
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: John Edward Barth, Jr., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
  • Patent number: 7982284
    Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
  • Patent number: 7968929
    Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Eric Thompson