Masterslice Integrated Circuit (epo) Patents (Class 257/E27.105)
  • Patent number: 11923296
    Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: March 5, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohito Suzumura, Kenichiro Sonoda, Hideaki Tsuchiya
  • Patent number: 11889777
    Abstract: A semiconductor memory device includes a first wiring to a fifth wiring, a plurality of memory cells disposed between the wirings, and a first contact electrode to a third contact electrode. The first contact electrode is disposed between the first wiring and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode is disposed between the first contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The third contact electrode is disposed between the second contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode has a width larger than a width of the first contact electrode and larger than a width of the third contact electrode.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Hiroyuki Ode, Kotaro Noda
  • Patent number: 11887976
    Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: January 30, 2024
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Yi-Jyun Lee
  • Patent number: 11189639
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Patent number: 10547313
    Abstract: A circuit arrangement, in particular for a safety I&C system of a nuclear power plant, keeps a proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement includes: a generic FPGA with a plurality of logic blocks, and at least one dedicated PLD which operates as an application-specific switch-matrix for the logic blocks.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 28, 2020
    Assignee: AREVA NP SAS
    Inventors: Guenther Auer, Johannes Weber
  • Patent number: 10452805
    Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou
  • Patent number: 10169520
    Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou
  • Patent number: 9628594
    Abstract: A mobile device includes a conductive element and a ground node. The conductive element is configured to be detected by a proximity sensor. A switch is coupled between the conductive element and ground node. The conductive element is coupled to the ground node by closing the switch. A first memory element is configured to control the switch. The first memory element includes a register bit coupled to a control terminal of the switch. A data output is configured to control the switch. A FIFO is configured to provide data to the data output. The first memory element includes a FIFO. A capacitive touch controller is configured to measure a capacitance of the conductive element. A digital processing unit is configured to convert the capacitance of the conductive element to a bit of data. A second memory element is configured to store the bit of data.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 18, 2017
    Assignee: Semtech Corporation
    Inventor: Chaouki Rouaissia
  • Patent number: 9373398
    Abstract: A method can include programming programmable resistive elements (PREs) in a first integrated circuit (IC) device to establish functions of configurable circuits of the first IC device; and creating at least one second IC device by forming non-programmable connections based on resistive states of the PREs of the first IC device to provide the functions of the first IC device in the second IC device.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: June 21, 2016
    Assignee: Adesto Technologies Corporation
    Inventor: Ishai Naveh
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8853815
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • Patent number: 8710553
    Abstract: An integrated circuit includes a substrate. The substrate includes diffusion lines. The diffusion lines include impurities diffused into the substrate. A signal line layer includes first signal lines. A first metal layer includes second signal lines. The second signal lines include a first metallic material. A second metal layer includes third signal lines. The third signal lines include a second metallic material. First contacts connect the diffusion lines to (i) a first set of the second signal lines, or (ii) a first set of the third signal lines. Second contacts connect a first set of the first signal lines to a second set of the third signal lines. Each signal line in a first set of the second signal lines includes first portions and second portions. The first portions extend towards and are not connected to the second contacts. The first portions are not parallel to the second portions.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Patent number: 8569860
    Abstract: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a planar type device isolation gate electrode, and a width of the planar type device isolation gate electrode greater than a width of the device gate electrode.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hee Yeom
  • Patent number: 8563986
    Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: October 22, 2013
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Publication number: 20130234210
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
  • Publication number: 20130193554
    Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Osamu S. Nakagawa, Moshtaque Yusuf
  • Patent number: 8482039
    Abstract: A memory array includes a first layer, a second layer, a third layer and a contact. The first layer is disposed on a substrate. The second layer includes a first conductive line. The first conductive line includes first line segments and second line segments. Each of the second line segments are connected to a respective one of the first line segments. The first line segments extend in a first direction on the first layer. The second line segments extend in a second direction on the first layer. The first direction is different than the second direction. The third layer is disposed on the second layer. The contact is disposed through the second layer and connects the third layer to the first conductive line. One of the first line segments extends towards the contact. Each of the first and second line segments are at least a predetermined distance from the contact.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 9, 2013
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Publication number: 20130161700
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: Nan Ya Technology Corporation
    Inventors: Panda Durga, Jaydip Guha, Robert Kerr
  • Patent number: 8441040
    Abstract: A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichi Minemura, Hiroyuki Nagashima
  • Patent number: 8354696
    Abstract: A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: January 15, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshiaki Shimizu, Kazuhiko Matsuki
  • Patent number: 8319277
    Abstract: A semiconductor device that includes multiple logic circuit cells having respective logic circuits formed therein and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Takahiro Kimura
  • Publication number: 20120280282
    Abstract: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.
    Type: Application
    Filed: January 29, 2010
    Publication date: November 8, 2012
    Inventors: Wei Wu, R. Stanley Williams
  • Publication number: 20120256234
    Abstract: First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.
    Type: Application
    Filed: March 22, 2012
    Publication date: October 11, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: HIDETOSHI NISHIMURA, TOMOAKI IKEGAMI
  • Patent number: 8278689
    Abstract: A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 2, 2012
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Publication number: 20120112245
    Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and (programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 10, 2012
    Applicant: CrossFire Technologies, Inc.
    Inventors: Kevin Atkinson, Clifford H. Boler
  • Publication number: 20120091510
    Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 19, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Hironobu TAOKA, Yusaku Ono
  • Patent number: 8124429
    Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 28, 2012
    Inventor: Richard Norman
  • Publication number: 20120037959
    Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tetsuya KATOU
  • Patent number: 8105900
    Abstract: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: January 31, 2012
    Assignee: Nanya Technology Corporation
    Inventors: Hung-Mine Tsai, Ching-Nan Hsiao, Chung-Lin Huang
  • Publication number: 20120008364
    Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.
    Type: Application
    Filed: November 1, 2010
    Publication date: January 12, 2012
    Applicant: MAXCHIP ELECTRONICS CORP.
    Inventors: Tung-Ming Lai, Teng-Feng Wang, Kai-An Hsueh
  • Patent number: 8022443
    Abstract: An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: September 20, 2011
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Patent number: 7960833
    Abstract: An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: June 14, 2011
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20110108888
    Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 12, 2011
    Applicant: NuPGA Corporation
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
  • Publication number: 20110084312
    Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 14, 2011
    Applicant: Tela Innovations, Inc.
    Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
  • Publication number: 20110073915
    Abstract: A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Tatsuya NARUSE
  • Publication number: 20110068373
    Abstract: A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.
    Type: Application
    Filed: September 20, 2010
    Publication date: March 24, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoichi MINEMURA, Hiroyuki Nagashima
  • Patent number: 7906800
    Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7893518
    Abstract: A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 22, 2011
    Assignee: Atmel Automotive GmbH
    Inventor: Martin Krauss
  • Publication number: 20110031535
    Abstract: A finger length al of a transistor P11 is longer than a finger length Al of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Toshiaki IWAMATSU
  • Publication number: 20110007541
    Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.
    Type: Application
    Filed: September 22, 2010
    Publication date: January 13, 2011
    Inventor: Roy E. Scheuerlein
  • Publication number: 20110006347
    Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 13, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Qiang Tang, Ramin Ghodsi
  • Patent number: 7825475
    Abstract: An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: November 2, 2010
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AG
    Inventors: Kiran V. Chatty, David Alvarez, Bong Jae Kwon, Christian C. Russ
  • Patent number: 7781804
    Abstract: A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: August 24, 2010
    Assignee: Nanya Technology Corporation
    Inventors: Hung-Mine Tsai, Ching-Nan Hsiao, Chung-Lin Huang
  • Patent number: 7755110
    Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: July 13, 2010
    Assignee: Infineon Technologies AG
    Inventors: Jörg Gliese, Winfried Kamp, Siegmar Köppe, Michael Scheppler
  • Patent number: 7696541
    Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
  • Patent number: 7683401
    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are formed in the active region. A gate electrode is located between the contact metals in the active region. A first distance between the active region and the dummy active region, and a second distance between an edge of the contact metal and an edge of the active region are set such that a channel characteristic of the active region is improved.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Jin Jung
  • Patent number: 7582921
    Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: September 1, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tomonori Sekiguchi, Toshihiko Tanaka, Toshiaki Yamanaka, Takeshi Sakata, Katsutaka Kimura
  • Publication number: 20090152593
    Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.
    Type: Application
    Filed: March 6, 2008
    Publication date: June 18, 2009
    Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
  • Patent number: 7521735
    Abstract: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, Leathen Shi
  • Patent number: 7476915
    Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: January 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masayuki Ohayashi, Takashi Yokoi