Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.

Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and crystallized using a metal catalyst, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to source and drain regions of the semiconductor layer through contact holes exposing predetermined regions of the source and drain regions of the semiconductor layer formed within the gate insulating layer and the interlayer insulating layer. A metal silicide including a metal that is different from the metal catalyst is present within a region of the semiconductor layer under the contact hole from the surface of the semiconductor layer to a predetermined depth.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and crystallized using a metal catalyst, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to source and drain regions of the semiconductor layer through contact holes exposing predetermined regions of the source and drain regions of the semiconductor layer formed within the gate insulating layer and the interlayer insulating layer. A metal silicide including a metal that is different from the metal catalyst is present within a region of the semiconductor layer under the contact hole from the surface of the semiconductor layer to a predetermined depth.

Abstract: A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the source terminal of the depletion mode FET are directly connected to each other. Additionally, the emitter terminal of the bipolar transistor and the gate terminal of the depletion mode FET are directly connected to each other. The voltage between the collector and emitter terminals, VCE, is configured to bias the depletion mode FET. The VCE voltage has a value that is equal and opposite to a voltage VGS between the gate and source terminals of the depletion mode FET.

Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.

Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

Abstract: The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Abstract: A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a current-sensing resistance for another of the devices; and a gate driver connected to the gates of the forward- and reverse-conducting devices for controlling the devices such that a channel of each of the devices simultaneously conducts a current.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.